core/stdarch/crates/core_arch/src/arm_shared/mod.rs
1//! ARM C Language Extensions (ACLE)
2//!
3//! # Developer notes
4//!
5//! Below is a list of built-in targets that are representative of the different ARM
6//! architectures; the list includes the `target_feature`s they possess.
7//!
8//! - `armv4t-unknown-linux-gnueabi` - **ARMv4** - `+v4t`
9//! - `armv5te-unknown-linux-gnueabi` - **ARMv5TE** - `+v4t +v5te`
10//! - `arm-unknown-linux-gnueabi` - **ARMv6** - `+v4t +v5te +v6`
11//! - `thumbv6m-none-eabi` - **ARMv6-M** - `+v4t +v5te +v6 +thumb-mode +mclass`
12//! - `armv7-unknown-linux-gnueabihf` - **ARMv7-A** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +aclass`
13//! - `armv7r-none-eabi` - **ARMv7-R** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +rclass`
14//! - `thumbv7m-none-eabi` - **ARMv7-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +thumb2 +thumb-mode +mclass`
15//! - `thumbv7em-none-eabi` - **ARMv7E-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +thumb-mode +mclass`
16//! - `thumbv8m.main-none-eabi` - **ARMv8-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +thumb2 +thumb-mode +mclass`
17//! - `armv8r-none-eabi` - **ARMv8-R** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +v8 +thumb2 +rclass`
18//! - `aarch64-unknown-linux-gnu` - **ARMv8-A (AArch64)** - `+fp +neon`
19//!
20//! Section 10.1 of ACLE says:
21//!
22//! - "In the sequence of Arm architectures { v5, v5TE, v6, v6T2, v7 } each architecture includes
23//! its predecessor instruction set."
24//!
25//! - "In the sequence of Thumb-only architectures { v6-M, v7-M, v7E-M } each architecture includes
26//! its predecessor instruction set."
27//!
28//! From that info and from looking at how LLVM features work (using custom targets) we can identify
29//! features that are subsets of others:
30//!
31//! Legend: `a < b` reads as "`a` is a subset of `b`"; this means that if `b` is enabled then `a` is
32//! enabled as well.
33//!
34//! - `v4t < v5te < v6 < v6k < v6t2 < v7 < v8`
35//! - `v6 < v8m < v6t2`
36//! - `v7 < v8m.main`
37//!
38//! *NOTE*: Section 5.4.7 of ACLE says:
39//!
40//! - "__ARM_FEATURE_DSP is defined to 1 if the DSP (v5E) instructions are supported and the
41//! intrinsics defined in Saturating intrinsics are available."
42//!
43//! This does *not* match how LLVM uses the '+dsp' feature; this feature is not set for v5te
44//! targets so we have to work around this difference.
45//!
46//! # References
47//!
48//! - [ACLE Q2 2018](https://developer.arm.com/docs/101028/latest)
49
50// Only for 'neon' submodule
51#![allow(non_camel_case_types)]
52
53// 8, 7 and 6-M are supported via dedicated instructions like DMB. All other arches are supported
54// via CP15 instructions. See Section 10.1 of ACLE
55mod barrier;
56#[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
57pub use self::barrier::*;
58
59mod hints;
60#[unstable(feature = "stdarch_arm_hints", issue = "117218")]
61pub use self::hints::*;
62
63#[cfg(any(
64 target_arch = "aarch64",
65 target_arch = "arm64ec",
66 target_feature = "v7",
67 doc
68))]
69pub(crate) mod neon;
70
71#[cfg(any(
72 target_arch = "aarch64",
73 target_arch = "arm64ec",
74 target_feature = "v7",
75 doc
76))]
77#[cfg_attr(
78 not(target_arch = "arm"),
79 stable(feature = "neon_intrinsics", since = "1.59.0")
80)]
81#[cfg_attr(
82 target_arch = "arm",
83 unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
84)]
85pub use self::neon::*;
86
87#[cfg(test)]
88#[cfg(any(
89 target_arch = "aarch64",
90 target_arch = "arm64ec",
91 target_feature = "v7",
92 doc
93))]
94pub(crate) mod test_support;
95
96mod sealed {
97 #[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
98 pub trait Dmb {
99 unsafe fn __dmb(&self);
100 }
101
102 #[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
103 pub trait Dsb {
104 unsafe fn __dsb(&self);
105 }
106
107 #[unstable(feature = "stdarch_arm_barrier", issue = "117219")]
108 pub trait Isb {
109 unsafe fn __isb(&self);
110 }
111}