0 00:00:00,000 --> 00:00:30,000 Dear viewer, these subtitles were generated by a machine via the service Trint and therefore are (very) buggy. If you are capable, please help us to create good quality subtitles: https://c3subtitles.de/talk/101 Thanks! 1 00:00:09,130 --> 00:00:11,229 So we are here to learn about 2 00:00:11,230 --> 00:00:13,149 field programing, gator race and custom 3 00:00:13,150 --> 00:00:14,859 Becca is going to is going to teach us 4 00:00:14,860 --> 00:00:16,989 how to do that so there can be more 5 00:00:16,990 --> 00:00:19,149 and merrier, you know, FPGA programmers 6 00:00:19,150 --> 00:00:20,709 because they can do more cool stuff. 7 00:00:21,760 --> 00:00:23,469 And I'm pleased to introduce my colleague 8 00:00:23,470 --> 00:00:25,029 and fellow part time scientist Carson 9 00:00:25,030 --> 00:00:26,030 Becker. 10 00:00:26,440 --> 00:00:28,809 He is a local Hamburg resident 11 00:00:28,810 --> 00:00:30,939 and Ph.D. candidate at the University 12 00:00:30,940 --> 00:00:31,940 of BookBook. 13 00:00:33,520 --> 00:00:35,879 And he learned to love FPGA 14 00:00:35,880 --> 00:00:38,139 A's after he he made his first 15 00:00:38,140 --> 00:00:40,869 3D graphics accelerator in university, 16 00:00:41,920 --> 00:00:44,079 and he continues to pursue this 17 00:00:44,080 --> 00:00:46,509 line of work in his dissertation. 18 00:00:46,510 --> 00:00:48,879 And he also solves 19 00:00:48,880 --> 00:00:51,219 FPGA programing and all other electronics 20 00:00:51,220 --> 00:00:53,439 problems for the Google Lunar Express 21 00:00:53,440 --> 00:00:55,509 team, the part time scientists 22 00:00:55,510 --> 00:00:57,369 who are still in the running to be the 23 00:00:57,370 --> 00:00:59,439 first private organization to put a 24 00:00:59,440 --> 00:01:00,440 rover on the Moon. 25 00:01:01,690 --> 00:01:03,189 So please welcome cousin Becca. 26 00:01:12,030 --> 00:01:13,409 OK, thanks a lot. 27 00:01:13,410 --> 00:01:15,239 I think the introduction was very slowly, 28 00:01:15,240 --> 00:01:18,419 so I can just skip this slide, 29 00:01:18,420 --> 00:01:20,849 so I'm going to talk about effigies 30 00:01:20,850 --> 00:01:22,529 because I really loved them a lot. 31 00:01:22,530 --> 00:01:24,659 And you can do 32 00:01:24,660 --> 00:01:26,579 really like everything with them. 33 00:01:26,580 --> 00:01:27,689 It's just very hard to do. 34 00:01:29,510 --> 00:01:31,049 No way I wanted to motivate you. 35 00:01:31,050 --> 00:01:32,849 It's not so hard, but you didn't need to 36 00:01:32,850 --> 00:01:34,919 know what you're doing, and I 37 00:01:34,920 --> 00:01:36,329 want to show you what you can do with 38 00:01:36,330 --> 00:01:38,639 those, what they read, they excel 39 00:01:38,640 --> 00:01:40,949 at and what are the use cases 40 00:01:40,950 --> 00:01:42,479 where they're not so good at? 41 00:01:42,480 --> 00:01:45,059 And essentially, what is an FPGA? 42 00:01:45,060 --> 00:01:47,159 It's the programable logic. 43 00:01:47,160 --> 00:01:49,319 So you can have you have an area that 44 00:01:49,320 --> 00:01:51,749 you can program and you can do 45 00:01:51,750 --> 00:01:53,729 whatever you want with this. 46 00:01:53,730 --> 00:01:55,949 So those are a few that know 47 00:01:55,950 --> 00:01:57,749 binary signals. 48 00:01:57,750 --> 00:02:00,119 You know that if you have something like 49 00:02:00,120 --> 00:02:02,219 two inputs, system like a C 50 00:02:02,220 --> 00:02:04,439 was two pins and one output, 51 00:02:04,440 --> 00:02:06,569 you can have four combinations 52 00:02:06,570 --> 00:02:07,889 at the inputs. 53 00:02:07,890 --> 00:02:10,110 And I would just call them A and B, and 54 00:02:11,130 --> 00:02:13,379 the combinations that you can see are 55 00:02:13,380 --> 00:02:14,999 very obvious. 56 00:02:15,000 --> 00:02:17,309 And the thing is and programable 57 00:02:17,310 --> 00:02:19,709 logic, you can set X 58 00:02:19,710 --> 00:02:20,710 to whatever you want. 59 00:02:22,320 --> 00:02:24,929 For example, on the left side, you see 60 00:02:24,930 --> 00:02:27,269 XOR that is realized that 61 00:02:27,270 --> 00:02:29,189 if you have zero zero as input output, as 62 00:02:29,190 --> 00:02:31,559 zero, if it has one and one, that's 63 00:02:31,560 --> 00:02:33,629 input output to zero and 64 00:02:33,630 --> 00:02:35,349 otherwise it will put a one on the right 65 00:02:35,350 --> 00:02:36,350 hand side, you see. 66 00:02:39,000 --> 00:02:40,000 I don't know. 67 00:02:41,340 --> 00:02:43,199 Yep. Perfect. 68 00:02:43,200 --> 00:02:45,059 And so you got the idea. 69 00:02:45,060 --> 00:02:46,080 So that's good. 70 00:02:48,750 --> 00:02:50,879 You know that you know that 71 00:02:50,880 --> 00:02:52,199 you can build and and you know that you 72 00:02:52,200 --> 00:02:54,329 can build like every logic circuit 73 00:02:54,330 --> 00:02:56,499 possible with just 74 00:02:56,500 --> 00:02:59,279 those lookup tables as they are called. 75 00:02:59,280 --> 00:03:01,919 So the the idea is that you have 76 00:03:01,920 --> 00:03:03,899 in an FPGA, you have you have those 77 00:03:03,900 --> 00:03:05,879 lookup tables where you have some inputs 78 00:03:05,880 --> 00:03:07,949 and you can describe what 79 00:03:07,950 --> 00:03:09,209 the output should be. 80 00:03:09,210 --> 00:03:11,759 And the fun begins when you realize 81 00:03:11,760 --> 00:03:14,789 that one of those outputs 82 00:03:14,790 --> 00:03:17,009 can be the input of another 83 00:03:17,010 --> 00:03:19,109 lookup table and then you create 84 00:03:19,110 --> 00:03:21,779 a network of lookup tables and 85 00:03:21,780 --> 00:03:24,089 then you can create even more complex 86 00:03:24,090 --> 00:03:25,090 logic. 87 00:03:25,920 --> 00:03:28,559 This is the basic idea how an FPGA 88 00:03:28,560 --> 00:03:29,560 works. 89 00:03:30,720 --> 00:03:32,789 In reality, it looks a 90 00:03:32,790 --> 00:03:34,559 bit different. 91 00:03:34,560 --> 00:03:36,209 Note how it says that this is a 92 00:03:36,210 --> 00:03:38,909 simplified vertex 93 00:03:38,910 --> 00:03:40,679 six slides. 94 00:03:40,680 --> 00:03:42,779 So what you can see the real full 95 00:03:42,780 --> 00:03:44,219 lookup tables on the left. 96 00:03:44,220 --> 00:03:46,409 Then there are some multiplexes which 97 00:03:46,410 --> 00:03:48,809 are selecting signals, 98 00:03:48,810 --> 00:03:50,579 and then there are some registers. 99 00:03:50,580 --> 00:03:52,889 And yeah, so 100 00:03:52,890 --> 00:03:55,009 it's not as trivial as I, as 101 00:03:55,010 --> 00:03:57,419 I may sound was just to look up tables. 102 00:03:57,420 --> 00:04:00,149 It's a bit more complicated, and 103 00:04:00,150 --> 00:04:02,399 I'm going to tell you a bit about 104 00:04:02,400 --> 00:04:03,400 it. 105 00:04:03,720 --> 00:04:06,419 So this 106 00:04:06,420 --> 00:04:07,469 was the lookup tables. 107 00:04:07,470 --> 00:04:09,659 You can, for example, make a very simple 108 00:04:09,660 --> 00:04:10,949 error and 109 00:04:11,970 --> 00:04:14,039 you can have an input signal that 110 00:04:14,040 --> 00:04:16,199 is like four bits and you add one and 111 00:04:16,200 --> 00:04:18,449 you get another output signal that is 112 00:04:18,450 --> 00:04:20,309 four bits as well. 113 00:04:20,310 --> 00:04:22,049 And the question is, how do you, for 114 00:04:22,050 --> 00:04:24,359 example, implement a counter 115 00:04:24,360 --> 00:04:26,429 if you just if you have if you use 116 00:04:26,430 --> 00:04:28,329 the input of your own, then there's the 117 00:04:28,330 --> 00:04:30,239 error and use the output of the error and 118 00:04:30,240 --> 00:04:32,339 feed it directly into the error 119 00:04:32,340 --> 00:04:34,409 as well. Then you have a combinatorial 120 00:04:34,410 --> 00:04:36,629 loop and 121 00:04:36,630 --> 00:04:38,189 it will do nothing useful. 122 00:04:39,630 --> 00:04:41,729 And to avoid that because 123 00:04:41,730 --> 00:04:42,929 you want to do something useful with 124 00:04:42,930 --> 00:04:45,089 FPGA, those 125 00:04:45,090 --> 00:04:47,069 so-called registers registers are like 126 00:04:47,070 --> 00:04:48,070 data storage. 127 00:04:50,670 --> 00:04:53,009 You know that your recipe, for example, 128 00:04:53,010 --> 00:04:55,139 has has a clock, and what 129 00:04:55,140 --> 00:04:57,299 it does is on every rising edge 130 00:04:57,300 --> 00:04:59,279 of the clock. It does something 131 00:04:59,280 --> 00:05:01,469 interesting its source, the data 132 00:05:01,470 --> 00:05:04,229 that is on the input and 133 00:05:04,230 --> 00:05:05,909 a little bit later, it puts it on the 134 00:05:05,910 --> 00:05:06,910 output 135 00:05:07,770 --> 00:05:08,939 and 136 00:05:08,940 --> 00:05:11,129 it just captures the inputs at the very 137 00:05:11,130 --> 00:05:13,229 specific, especially at the very 138 00:05:13,230 --> 00:05:15,449 specific moment of the rising 139 00:05:15,450 --> 00:05:16,439 edge. 140 00:05:16,440 --> 00:05:18,959 And with it, you can have 141 00:05:18,960 --> 00:05:20,859 you can have your logic that is, you 142 00:05:20,860 --> 00:05:22,799 know, combinatorial logic with input 143 00:05:22,800 --> 00:05:25,079 tables over the lookup tables and 144 00:05:25,080 --> 00:05:27,389 put that into a register 145 00:05:27,390 --> 00:05:29,249 and then you have another portion of 146 00:05:29,250 --> 00:05:30,779 combinatorial logic. 147 00:05:30,780 --> 00:05:32,819 And then you can have another register, 148 00:05:32,820 --> 00:05:34,949 for example, or you can create a feedback 149 00:05:34,950 --> 00:05:37,439 loop. For example, if you want to realize 150 00:05:37,440 --> 00:05:40,349 a counter, you have your 151 00:05:40,350 --> 00:05:43,079 you have your four digits and 152 00:05:43,080 --> 00:05:45,809 you add one in your combinatorial 153 00:05:45,810 --> 00:05:48,119 logic and you put it as a new input 154 00:05:48,120 --> 00:05:51,119 for the for the register. 155 00:05:51,120 --> 00:05:53,699 And the reason this works is because 156 00:05:53,700 --> 00:05:55,859 the time it takes for the company, for 157 00:05:55,860 --> 00:05:58,049 the company to have 158 00:05:58,050 --> 00:05:59,489 the time it takes for the computer. 159 00:05:59,490 --> 00:06:01,290 Logic is not 160 00:06:02,850 --> 00:06:04,949 small, not 161 00:06:04,950 --> 00:06:07,139 infinitesimally small, but has 162 00:06:07,140 --> 00:06:08,429 a certain delay. 163 00:06:08,430 --> 00:06:09,929 And so it will arrive. 164 00:06:11,880 --> 00:06:14,249 You're the ideal you arrive for 165 00:06:14,250 --> 00:06:16,409 the next rising edge, but after 166 00:06:16,410 --> 00:06:18,719 the rising, it's actually occurred. 167 00:06:18,720 --> 00:06:20,339 And so this way you can create the 168 00:06:20,340 --> 00:06:21,360 counter and 169 00:06:23,550 --> 00:06:25,619 this way you can realize all kinds 170 00:06:25,620 --> 00:06:27,429 of interesting synchronous designs. 171 00:06:27,430 --> 00:06:29,369 For example, you can you can create as if 172 00:06:29,370 --> 00:06:31,559 you visit and do some other 173 00:06:31,560 --> 00:06:33,629 fun stuff, and I will talk about what 174 00:06:33,630 --> 00:06:35,429 you can do with it later. 175 00:06:35,430 --> 00:06:37,949 And especially, I will talk about why 176 00:06:37,950 --> 00:06:40,229 an FPGA can beat an A7 177 00:06:40,230 --> 00:06:42,389 in certain tasks, even 178 00:06:42,390 --> 00:06:43,979 though it is running at a frequency that 179 00:06:43,980 --> 00:06:45,060 is significantly lower 180 00:06:46,320 --> 00:06:48,719 than what the A7 181 00:06:48,720 --> 00:06:49,720 is running at. 182 00:06:51,470 --> 00:06:53,599 So when you have a look, when 183 00:06:53,600 --> 00:06:55,819 you have a ship, you have like three 184 00:06:55,820 --> 00:06:58,549 tasks A, B and C, and 185 00:06:58,550 --> 00:07:01,609 you can sequentially execute those 186 00:07:01,610 --> 00:07:03,739 and if you want to 187 00:07:03,740 --> 00:07:06,169 decrease the time, but for 188 00:07:06,170 --> 00:07:07,820 that it takes for those three tasks. 189 00:07:08,930 --> 00:07:10,759 You can actually increase the frequency 190 00:07:10,760 --> 00:07:13,159 of the of the ships you 191 00:07:13,160 --> 00:07:15,529 or you can make the task shorter by, 192 00:07:15,530 --> 00:07:17,839 you know, making them more efficient 193 00:07:19,220 --> 00:07:22,219 in an FPGA, you have actually 194 00:07:22,220 --> 00:07:24,889 something like a blank canvas. 195 00:07:24,890 --> 00:07:27,799 And in this canvas, you control your 196 00:07:27,800 --> 00:07:28,909 your functions. 197 00:07:28,910 --> 00:07:31,039 So for example, on the upper left corner, 198 00:07:31,040 --> 00:07:33,139 you can place like, you know, eight motor 199 00:07:33,140 --> 00:07:35,209 controllers on the lower left 200 00:07:35,210 --> 00:07:37,609 corner. You place your ship you on 201 00:07:37,610 --> 00:07:39,889 or maybe because 202 00:07:39,890 --> 00:07:41,959 of its more force, if you but 203 00:07:41,960 --> 00:07:43,769 and maybe on the sea, you have your video 204 00:07:43,770 --> 00:07:46,879 decoder or encoding algorithm. 205 00:07:46,880 --> 00:07:48,979 And so the the thing 206 00:07:48,980 --> 00:07:51,979 that you're working with in an FPGA 207 00:07:51,980 --> 00:07:54,379 is actually the area and 208 00:07:54,380 --> 00:07:56,479 the frequency, the 209 00:07:56,480 --> 00:07:58,159 frequency that you can run your circuit 210 00:07:58,160 --> 00:08:00,859 that is determined at the first 211 00:08:00,860 --> 00:08:03,019 combinatorial delay that you have in your 212 00:08:03,020 --> 00:08:04,069 whole design. 213 00:08:05,660 --> 00:08:07,879 So for example, if you if you want 214 00:08:07,880 --> 00:08:09,169 to compute. 215 00:08:09,170 --> 00:08:10,339 So for example, you are running the 216 00:08:10,340 --> 00:08:12,769 circuit, that's 10 megahertz. 217 00:08:12,770 --> 00:08:15,439 And so you have a certain amount of time 218 00:08:15,440 --> 00:08:17,749 between the rising edges of the clocks 219 00:08:17,750 --> 00:08:20,779 where the edges are starting the data. 220 00:08:20,780 --> 00:08:23,329 And if you're exceeding if your 221 00:08:23,330 --> 00:08:25,669 if your audition exceeds this time, 222 00:08:25,670 --> 00:08:27,769 then your timing is not 223 00:08:27,770 --> 00:08:30,859 met and you cannot use 224 00:08:30,860 --> 00:08:33,019 the design that you have chosen to 225 00:08:33,020 --> 00:08:34,308 run with this frequency. 226 00:08:34,309 --> 00:08:36,139 You have to lower the frequency. 227 00:08:36,140 --> 00:08:37,879 This may be possible if your design 228 00:08:37,880 --> 00:08:38,808 allows it. 229 00:08:38,809 --> 00:08:40,249 Most of the time it does not because you 230 00:08:40,250 --> 00:08:42,619 are constrained by, you know, 231 00:08:42,620 --> 00:08:43,759 some external clock. 232 00:08:43,760 --> 00:08:45,949 Or maybe you're doing you as B 233 00:08:45,950 --> 00:08:48,199 data transfer or you have a camera 234 00:08:48,200 --> 00:08:49,639 that is collecting your data into the 235 00:08:49,640 --> 00:08:50,640 FPGA. 236 00:08:52,100 --> 00:08:54,079 So in this case, you need to split up the 237 00:08:54,080 --> 00:08:56,719 combinatorial logic into smaller blocks 238 00:08:56,720 --> 00:08:59,059 and distribute them so that 239 00:08:59,060 --> 00:09:00,949 and the one cycles you are doing the part 240 00:09:00,950 --> 00:09:02,629 of the addition and the next cycle you're 241 00:09:02,630 --> 00:09:05,389 doing the next part of the addition. 242 00:09:05,390 --> 00:09:07,039 And so that you can increase your 243 00:09:07,040 --> 00:09:09,529 frequency and you can 244 00:09:09,530 --> 00:09:11,659 and area is also very difficult 245 00:09:12,770 --> 00:09:14,629 if you are if you're using if you're 246 00:09:14,630 --> 00:09:16,579 making blocks smaller, sometimes you're 247 00:09:16,580 --> 00:09:19,369 increasing the area that it consumes. 248 00:09:19,370 --> 00:09:20,989 And when your 249 00:09:22,030 --> 00:09:23,329 when your area is consumed, you need to 250 00:09:23,330 --> 00:09:24,559 buy a bigger device 251 00:09:25,670 --> 00:09:27,199 so you can. 252 00:09:27,200 --> 00:09:29,359 Yeah. So this is like the bigger device 253 00:09:29,360 --> 00:09:31,729 obviously are more expensive as 254 00:09:31,730 --> 00:09:32,730 smaller devices. 255 00:09:35,630 --> 00:09:38,269 So in reality, 256 00:09:38,270 --> 00:09:40,919 it's not just the look up table said 257 00:09:40,920 --> 00:09:43,099 that this so-called fabric, which 258 00:09:43,100 --> 00:09:45,559 is the programable part of the FPGA, 259 00:09:45,560 --> 00:09:47,209 is composed of actually. 260 00:09:47,210 --> 00:09:49,339 It also contains the lookup tables, the 261 00:09:49,340 --> 00:09:50,340 flip flops 262 00:09:53,710 --> 00:09:55,879 or the data storage registers 263 00:09:55,880 --> 00:09:58,169 as they call them, but also contain 264 00:09:58,170 --> 00:10:00,259 some multiplexes where you are selecting 265 00:10:00,260 --> 00:10:02,419 between several input signals. 266 00:10:03,440 --> 00:10:04,999 It contains rotting resources, which are 267 00:10:05,000 --> 00:10:07,249 very important if you're 268 00:10:07,250 --> 00:10:08,959 if you have a look up table here and you 269 00:10:08,960 --> 00:10:10,369 have another look up table here and they 270 00:10:10,370 --> 00:10:11,629 should be connected. 271 00:10:11,630 --> 00:10:14,479 Then there is there are very fast 272 00:10:14,480 --> 00:10:16,519 connections between those and those are 273 00:10:16,520 --> 00:10:17,629 your routing resources. 274 00:10:18,800 --> 00:10:20,959 And obviously, you can also run out 275 00:10:20,960 --> 00:10:22,159 of those. 276 00:10:22,160 --> 00:10:24,169 Usually you will also find some clock 277 00:10:24,170 --> 00:10:26,269 management things like 278 00:10:26,270 --> 00:10:28,249 like a parallel where you can have input 279 00:10:28,250 --> 00:10:30,469 a frequency of 10 megahertz 280 00:10:30,470 --> 00:10:32,089 and get all the frequency of, you know, 281 00:10:32,090 --> 00:10:33,090 whatever you like. 282 00:10:33,950 --> 00:10:35,539 Usually 20 megahertz or something like 283 00:10:35,540 --> 00:10:38,029 this. Then there is also 284 00:10:38,030 --> 00:10:40,399 Kerry Logic, which helps you to 285 00:10:40,400 --> 00:10:42,709 to create faster multipliers and 286 00:10:42,710 --> 00:10:44,989 errors, which is very important, and 287 00:10:44,990 --> 00:10:46,609 shift registers which are used for 288 00:10:46,610 --> 00:10:47,610 shifting a bit 289 00:10:48,890 --> 00:10:50,239 to either direction. 290 00:10:52,310 --> 00:10:54,769 In theory, you could realize 291 00:10:54,770 --> 00:10:56,839 a lot or almost everything 292 00:10:56,840 --> 00:10:58,909 was just those components that 293 00:10:58,910 --> 00:11:01,069 you find on the left hand side. 294 00:11:01,070 --> 00:11:02,070 But the problem is 295 00:11:03,230 --> 00:11:05,479 making a making a CPU is just 296 00:11:05,480 --> 00:11:07,549 those components is not 297 00:11:07,550 --> 00:11:08,539 very efficient. 298 00:11:08,540 --> 00:11:10,639 And so the windows went on to decide 299 00:11:10,640 --> 00:11:12,799 like, OK, maybe it's a good idea 300 00:11:12,800 --> 00:11:14,929 to, for example, add a 301 00:11:14,930 --> 00:11:15,859 hardware multiplier. 302 00:11:15,860 --> 00:11:18,109 You know, it consumes 303 00:11:18,110 --> 00:11:20,359 significantly less space on the 304 00:11:20,360 --> 00:11:21,289 on the die. 305 00:11:21,290 --> 00:11:23,209 Then if you have if you're doing it, 306 00:11:23,210 --> 00:11:25,279 there is lookup tables and it's also 307 00:11:25,280 --> 00:11:27,229 to run significant faster. 308 00:11:27,230 --> 00:11:29,569 And so they decided 309 00:11:29,570 --> 00:11:31,339 to put all kinds of interesting stuff 310 00:11:31,340 --> 00:11:33,619 into what's called hot blocks 311 00:11:33,620 --> 00:11:35,209 or hot cores. 312 00:11:35,210 --> 00:11:37,729 And one of those is, for example, the DSP 313 00:11:37,730 --> 00:11:39,919 unit, which which is actually a 314 00:11:39,920 --> 00:11:41,899 multiply accumulates. 315 00:11:41,900 --> 00:11:43,549 You can use those for all kinds of 316 00:11:43,550 --> 00:11:46,849 interesting folders and stuff, and 317 00:11:46,850 --> 00:11:49,039 then our multipliers are very popular 318 00:11:49,040 --> 00:11:50,539 18 18 bit by 18. 319 00:11:50,540 --> 00:11:51,629 But. 320 00:11:51,630 --> 00:11:52,769 Very popular and with. 321 00:11:53,790 --> 00:11:55,829 You may notice that every vendors don't 322 00:11:55,830 --> 00:11:58,019 really care much about eight, 16 or 323 00:11:58,020 --> 00:12:00,209 32, but they care more 324 00:12:00,210 --> 00:12:01,409 about it. 325 00:12:01,410 --> 00:12:03,479 But, you know, I 326 00:12:03,480 --> 00:12:05,699 don't know why they shows 327 00:12:05,700 --> 00:12:06,900 probably have a good reason for. 328 00:12:07,950 --> 00:12:10,769 You will also find block rum, which is 329 00:12:10,770 --> 00:12:13,859 which is run that is embedded into the 330 00:12:13,860 --> 00:12:16,529 into the fabric so that you can have some 331 00:12:16,530 --> 00:12:17,530 storage, 332 00:12:18,600 --> 00:12:20,369 some bigger stores there are like 333 00:12:20,370 --> 00:12:22,589 multiroom megabit, sometimes 334 00:12:22,590 --> 00:12:25,079 if you're like buying a really expensive 335 00:12:25,080 --> 00:12:26,489 FPGA. 336 00:12:26,490 --> 00:12:29,459 Sometimes they are just a few kilobits 337 00:12:29,460 --> 00:12:31,549 and also you have some high speed 338 00:12:31,550 --> 00:12:33,659 interfaces. For example, with an FPGA, 339 00:12:33,660 --> 00:12:35,849 you can you can attach 340 00:12:35,850 --> 00:12:38,429 to a PCI Express port and 341 00:12:38,430 --> 00:12:40,889 connect with those, or you can 342 00:12:40,890 --> 00:12:43,319 you can attach your own SATA 343 00:12:43,320 --> 00:12:46,169 hut to scored your own slot or whatever 344 00:12:46,170 --> 00:12:47,429 and they can. 345 00:12:47,430 --> 00:12:49,499 The high speeds is really high speed 346 00:12:49,500 --> 00:12:52,139 because they can go up to like 25 347 00:12:52,140 --> 00:12:53,369 gigabits. 348 00:12:53,370 --> 00:12:54,370 Could I sense 349 00:12:55,470 --> 00:12:57,569 also some when I saw that, you know, 350 00:12:57,570 --> 00:12:59,039 it is really a good idea to embed the 351 00:12:59,040 --> 00:13:01,109 processor into the into the 352 00:13:01,110 --> 00:13:03,449 fabric or into the into the FPGA, 353 00:13:03,450 --> 00:13:05,939 which I think is a really smart idea 354 00:13:05,940 --> 00:13:08,369 because then you can have your 355 00:13:08,370 --> 00:13:10,859 software running on those if you but 356 00:13:10,860 --> 00:13:13,619 accelerate some functions in 357 00:13:13,620 --> 00:13:15,689 with the vista fabric. 358 00:13:15,690 --> 00:13:17,279 And I'm going to explain to you a bit 359 00:13:17,280 --> 00:13:19,409 about this later. 360 00:13:19,410 --> 00:13:20,759 Also, there are some memory controllers 361 00:13:20,760 --> 00:13:22,559 so that you can interface external 362 00:13:22,560 --> 00:13:25,559 memories like DDR video or. 363 00:13:25,560 --> 00:13:26,560 They all supporters 364 00:13:28,140 --> 00:13:30,659 and some winners also include some 365 00:13:30,660 --> 00:13:33,059 AC DC so that you can 366 00:13:33,060 --> 00:13:35,399 really meet, read some analog 367 00:13:35,400 --> 00:13:37,439 voltages or generate some analog what it 368 00:13:37,440 --> 00:13:38,440 really is. 369 00:13:39,720 --> 00:13:40,619 And I'm going to talk. 370 00:13:40,620 --> 00:13:42,419 I want to show you, I want to motivate 371 00:13:42,420 --> 00:13:44,669 you. What you can do with was 372 00:13:44,670 --> 00:13:46,589 FPGA, js and I was looking for some 373 00:13:46,590 --> 00:13:48,179 projects from the legacy that I really 374 00:13:48,180 --> 00:13:50,399 liked. And one of those projects is 375 00:13:50,400 --> 00:13:51,600 actually the bulk ventilator. 376 00:13:52,980 --> 00:13:55,229 It's hmm. 377 00:13:55,230 --> 00:13:56,399 I'm going to show you a picture first and 378 00:13:56,400 --> 00:13:57,709 then I'm going to come back to 379 00:13:57,710 --> 00:13:58,799 experimenters. 380 00:13:58,800 --> 00:14:00,779 So essentially, it's like it's like a 381 00:14:00,780 --> 00:14:01,769 ventilator. 382 00:14:01,770 --> 00:14:03,989 But instead of sending air, 383 00:14:03,990 --> 00:14:06,689 it's a serving spinning piece and 384 00:14:06,690 --> 00:14:08,879 there are like 250 LEDs. 385 00:14:10,050 --> 00:14:12,299 And then you can 386 00:14:13,800 --> 00:14:16,049 then you can attach any video source 387 00:14:16,050 --> 00:14:17,849 to it and it can be displayed. 388 00:14:17,850 --> 00:14:20,069 And what the FPGA is doing is 389 00:14:20,070 --> 00:14:21,569 it's, for example, are doing a particular 390 00:14:21,570 --> 00:14:23,979 transformation to to 391 00:14:23,980 --> 00:14:26,129 pull out coding. This is also doing 392 00:14:26,130 --> 00:14:28,409 some camera correction, 393 00:14:28,410 --> 00:14:31,709 and obviously it needs to do some very, 394 00:14:31,710 --> 00:14:33,869 very precise timing so that so 395 00:14:33,870 --> 00:14:36,629 the review is not stuttering around, but 396 00:14:36,630 --> 00:14:38,429 is really showing it 397 00:14:39,480 --> 00:14:40,439 at the same position. 398 00:14:40,440 --> 00:14:41,440 Always. 399 00:14:44,060 --> 00:14:46,339 Another very cool project that 400 00:14:46,340 --> 00:14:48,439 there was demoed like two years 401 00:14:48,440 --> 00:14:50,839 ago, I found that very, very cool 402 00:14:50,840 --> 00:14:52,999 because what 403 00:14:53,000 --> 00:14:55,609 he did was he used 404 00:14:55,610 --> 00:14:57,859 an HDMI input signal 405 00:14:57,860 --> 00:15:00,259 and he did not decode 406 00:15:00,260 --> 00:15:02,509 the signal itself, but 407 00:15:02,510 --> 00:15:04,969 he just sent up to the HD email signal 408 00:15:04,970 --> 00:15:07,169 and it puts it put 409 00:15:07,170 --> 00:15:09,259 in some encrypted overlay 410 00:15:09,260 --> 00:15:10,489 into the stream itself. 411 00:15:10,490 --> 00:15:12,319 So at one point, it was the original 412 00:15:12,320 --> 00:15:13,249 picture. 413 00:15:13,250 --> 00:15:15,439 And at some other point in time, it was 414 00:15:15,440 --> 00:15:17,719 another picture, and he 415 00:15:17,720 --> 00:15:19,879 expected the the key 416 00:15:19,880 --> 00:15:21,949 and inserted the encrypted stream. 417 00:15:21,950 --> 00:15:24,949 And the funny thing about is that he 418 00:15:24,950 --> 00:15:27,259 he does not need to decrypt the content 419 00:15:27,260 --> 00:15:29,359 stream, which is a pretty neat trick 420 00:15:29,360 --> 00:15:31,969 to avoid the dismay or DMCA 421 00:15:33,980 --> 00:15:36,049 lawsuits, because this would 422 00:15:36,050 --> 00:15:38,239 violate us if he was the key that 423 00:15:38,240 --> 00:15:39,830 was leaked several years ago. 424 00:15:41,300 --> 00:15:43,369 So the question is, how 425 00:15:43,370 --> 00:15:45,570 do you program and FPGA? 426 00:15:47,450 --> 00:15:49,879 Well, OK, so 427 00:15:49,880 --> 00:15:51,009 this is where it goes. 428 00:15:51,010 --> 00:15:53,239 OK, I want to play 429 00:15:53,240 --> 00:15:54,859 with you. This is where it gets fun. 430 00:15:54,860 --> 00:15:55,860 So. 431 00:15:56,750 --> 00:15:59,119 So you're you could easily choose 432 00:15:59,120 --> 00:16:01,369 a high level tool like 433 00:16:01,370 --> 00:16:02,749 MATLAB signaling. 434 00:16:02,750 --> 00:16:04,969 If you're coming from, you know, 435 00:16:04,970 --> 00:16:06,860 if you have this installed, 436 00:16:07,870 --> 00:16:08,899 you can install it. 437 00:16:08,900 --> 00:16:11,299 You can create really nice filters or 438 00:16:11,300 --> 00:16:13,189 test runs. 439 00:16:13,190 --> 00:16:15,559 Also, there is a very poor attempt of 440 00:16:15,560 --> 00:16:17,869 converting automatically converting C to 441 00:16:17,870 --> 00:16:19,939 audio, and the windows are like, This 442 00:16:19,940 --> 00:16:21,529 is the best idea ever. 443 00:16:21,530 --> 00:16:22,530 No, it's not, 444 00:16:23,840 --> 00:16:25,669 at least for the next 10 years. 445 00:16:25,670 --> 00:16:27,559 So don't do that. 446 00:16:27,560 --> 00:16:29,989 There is a there's attempts of 447 00:16:29,990 --> 00:16:32,329 porting open code to 448 00:16:32,330 --> 00:16:34,549 audio or through a for description 449 00:16:34,550 --> 00:16:36,709 language, which I think might 450 00:16:36,710 --> 00:16:37,609 actually work. 451 00:16:37,610 --> 00:16:39,739 And it's might not be the might 452 00:16:39,740 --> 00:16:41,989 not be as worse as trying to say, 453 00:16:41,990 --> 00:16:43,669 just give me a second and I will make, 454 00:16:43,670 --> 00:16:46,189 uh, make it faster on the FPGA, 455 00:16:46,190 --> 00:16:48,289 which will not always, never 456 00:16:48,290 --> 00:16:49,290 be true. 457 00:16:50,840 --> 00:16:52,999 And so this is 458 00:16:53,000 --> 00:16:55,099 a very high level, very constant. 459 00:16:55,100 --> 00:16:57,379 Also, you can start at at 460 00:16:57,380 --> 00:16:59,629 the description level, which is what is 461 00:16:59,630 --> 00:17:01,369 most commonly used these days. 462 00:17:03,290 --> 00:17:05,029 Unfortunately, a rather 463 00:17:06,500 --> 00:17:08,239 poor choice of languages have been 464 00:17:08,240 --> 00:17:10,339 established in the space of programing 465 00:17:11,450 --> 00:17:13,879 video and very look, both 466 00:17:13,880 --> 00:17:15,260 very old languages. 467 00:17:16,550 --> 00:17:18,679 Neither of them are nice to 468 00:17:18,680 --> 00:17:19,910 write, in my opinion. 469 00:17:21,140 --> 00:17:23,239 I'm going to show you, I'm 470 00:17:23,240 --> 00:17:24,799 going to show you examples first and then 471 00:17:24,800 --> 00:17:26,449 you'll see why I'm ranting about it. 472 00:17:26,450 --> 00:17:28,669 So as you can see on the left 473 00:17:28,670 --> 00:17:31,189 side, you will see VIDEO. 474 00:17:31,190 --> 00:17:33,259 It's for the military contractor 475 00:17:33,260 --> 00:17:34,939 to about among you. 476 00:17:34,940 --> 00:17:36,979 This is Aadhaar based. 477 00:17:36,980 --> 00:17:38,479 It's not like anyone cares about order, 478 00:17:38,480 --> 00:17:40,549 but this is 479 00:17:40,550 --> 00:17:43,009 video that's it has the same awfulness 480 00:17:43,010 --> 00:17:44,010 as other. 481 00:17:44,660 --> 00:17:46,759 It's very odd that you place all 482 00:17:46,760 --> 00:17:48,889 the semicolons there and not there and 483 00:17:48,890 --> 00:17:50,329 then the comma there and then you say and 484 00:17:50,330 --> 00:17:51,410 there, but not there, and 485 00:17:53,150 --> 00:17:54,499 it's very verbose as well. 486 00:17:55,730 --> 00:17:58,279 This makes it very confusing. 487 00:17:58,280 --> 00:17:59,280 I think 488 00:18:01,790 --> 00:18:03,500 there's lots of very liquid, just like 489 00:18:04,820 --> 00:18:06,999 they sound like, OK, if you show a 490 00:18:07,000 --> 00:18:09,109 by the way, Bechdel was not invented 491 00:18:09,110 --> 00:18:11,719 for programing FPGAs, 492 00:18:11,720 --> 00:18:14,119 but it was invented for documenting 493 00:18:14,120 --> 00:18:15,949 documenting the A6. 494 00:18:15,950 --> 00:18:18,259 And so at one point they sound like, 495 00:18:18,260 --> 00:18:20,779 hmm. If we are doing all the effort of, 496 00:18:20,780 --> 00:18:23,179 you know, describing it, why shouldn't 497 00:18:23,180 --> 00:18:25,819 we like simulators? 498 00:18:25,820 --> 00:18:28,489 And so they used video for simulation, 499 00:18:28,490 --> 00:18:30,649 and then they realize like, hmm, 500 00:18:30,650 --> 00:18:32,449 every like simulating it. 501 00:18:32,450 --> 00:18:34,489 We could actually use it, like for 502 00:18:34,490 --> 00:18:36,889 synthesis to put it on, on the left 503 00:18:36,890 --> 00:18:39,079 or on the on the async. 504 00:18:39,080 --> 00:18:41,329 And so, 505 00:18:41,330 --> 00:18:43,399 you know, actually, you could just use 506 00:18:43,400 --> 00:18:44,749 HDMI. 507 00:18:44,750 --> 00:18:45,919 It's, you know, it's like you're 508 00:18:45,920 --> 00:18:48,139 describing something and 509 00:18:48,140 --> 00:18:49,819 half of what you're describing cannot be 510 00:18:49,820 --> 00:18:52,279 synthesized to the FPGA, 511 00:18:52,280 --> 00:18:53,869 which is a problem that we actually have 512 00:18:53,870 --> 00:18:54,870 a very low cost sharing. 513 00:18:56,450 --> 00:18:58,759 And I think this is very 514 00:18:58,760 --> 00:19:00,979 confusing, but virtual is very 515 00:19:00,980 --> 00:19:03,499 popular in Europe and 516 00:19:03,500 --> 00:19:05,269 very, very low is very popular in the 517 00:19:05,270 --> 00:19:06,799 U.S. it's like a 50 50 split. 518 00:19:08,000 --> 00:19:10,159 I've heard that China is copying 519 00:19:10,160 --> 00:19:11,160 very OK. 520 00:19:13,640 --> 00:19:15,739 So yeah, 521 00:19:15,740 --> 00:19:17,449 and those are OK. 522 00:19:17,450 --> 00:19:18,529 Shameless plug of myself. 523 00:19:18,530 --> 00:19:20,149 There is also appears HDL, which is 524 00:19:20,150 --> 00:19:21,619 called the plain simple transcription 525 00:19:21,620 --> 00:19:22,699 language. 526 00:19:22,700 --> 00:19:25,069 You know, the same is the same code as 527 00:19:25,070 --> 00:19:26,659 you can see on the on the left, on the 528 00:19:26,660 --> 00:19:27,660 bottom. 529 00:19:28,160 --> 00:19:30,379 It's just shorter and not as 530 00:19:30,380 --> 00:19:31,640 fucked up as the others. 531 00:19:34,130 --> 00:19:35,599 Yeah, sorry. I really hate. 532 00:19:35,600 --> 00:19:38,179 You know, it's I've been working on 533 00:19:38,180 --> 00:19:40,399 at a university for quite a long time and 534 00:19:40,400 --> 00:19:42,279 I've been doing. 535 00:19:42,280 --> 00:19:43,389 What's called the hot property column 536 00:19:43,390 --> 00:19:45,549 every year, and maybe there 537 00:19:45,550 --> 00:19:47,259 are some students in the audience that 538 00:19:47,260 --> 00:19:49,729 are suffering from it right now. 539 00:19:49,730 --> 00:19:51,669 And it's every year it's the same, you 540 00:19:51,670 --> 00:19:53,469 know, people are struggling with tools 541 00:19:53,470 --> 00:19:55,749 struggling with was the language 542 00:19:55,750 --> 00:19:57,759 because it's not. So we don't know. 543 00:19:57,760 --> 00:20:00,069 I wonder what if is 544 00:20:00,070 --> 00:20:01,070 OK, never mind. 545 00:20:03,550 --> 00:20:05,809 So after you described 546 00:20:05,810 --> 00:20:08,169 your, you're designed 547 00:20:08,170 --> 00:20:09,369 with those beautiful words, 548 00:20:11,020 --> 00:20:12,669 the sentences to run among, it's 549 00:20:12,670 --> 00:20:14,109 unrealistic. 550 00:20:14,110 --> 00:20:15,189 Hmm. 551 00:20:15,190 --> 00:20:18,099 This piece that was described here versus 552 00:20:18,100 --> 00:20:20,169 ten thousand words looks 553 00:20:20,170 --> 00:20:22,659 like it's like an editor. 554 00:20:22,660 --> 00:20:25,059 So I will place and edit here, 555 00:20:25,060 --> 00:20:27,189 and then it will go around and 556 00:20:27,190 --> 00:20:29,049 do this for all the code. 557 00:20:29,050 --> 00:20:31,149 And sometimes it's guessing wrong. 558 00:20:31,150 --> 00:20:32,919 So you need to find you need to find 559 00:20:32,920 --> 00:20:35,259 those those kinds of 560 00:20:35,260 --> 00:20:37,029 features where it goes wrong. 561 00:20:37,030 --> 00:20:38,649 And then you have what's called a 562 00:20:38,650 --> 00:20:39,650 synthesis. 563 00:20:40,240 --> 00:20:41,530 And the synthesis actually 564 00:20:42,610 --> 00:20:43,780 translates to 565 00:20:44,890 --> 00:20:46,989 the words you have written into into 566 00:20:46,990 --> 00:20:49,119 blogs that can be placed on 567 00:20:49,120 --> 00:20:51,269 an FPGA or 568 00:20:51,270 --> 00:20:52,269 into a lookup table. 569 00:20:52,270 --> 00:20:55,149 It's multiplexes shift suffrages 570 00:20:55,150 --> 00:20:57,369 and all that stuff. 571 00:20:57,370 --> 00:20:59,319 And the result is a net list. 572 00:21:00,370 --> 00:21:02,919 And after that, 573 00:21:02,920 --> 00:21:05,079 this process is rather 574 00:21:05,080 --> 00:21:07,179 quick. It usually doesn't take more than 575 00:21:07,180 --> 00:21:08,559 two minutes. 576 00:21:08,560 --> 00:21:10,699 Um, and this is really 577 00:21:10,700 --> 00:21:11,859 quick. 578 00:21:11,860 --> 00:21:14,199 So and then comes the process of placing 579 00:21:14,200 --> 00:21:15,200 road. 580 00:21:16,630 --> 00:21:18,489 If you're used to slow compilers, you 581 00:21:18,490 --> 00:21:20,559 will appreciate the vastness of 582 00:21:20,560 --> 00:21:22,989 a modern C++ compiler. 583 00:21:22,990 --> 00:21:24,699 Once you realize that your place in road 584 00:21:24,700 --> 00:21:26,739 can, anywhere can take anywhere from one 585 00:21:26,740 --> 00:21:28,150 minute up to three weeks. 586 00:21:31,180 --> 00:21:32,180 The problem is. 587 00:21:35,650 --> 00:21:36,650 The problem is that 588 00:21:38,170 --> 00:21:40,479 placing the resources on an FPGA 589 00:21:40,480 --> 00:21:42,549 is an NP complete problem 590 00:21:42,550 --> 00:21:44,709 and fitting it into 591 00:21:44,710 --> 00:21:46,029 the timing that you are setting, for 592 00:21:46,030 --> 00:21:47,709 example, you say at one point you're 593 00:21:47,710 --> 00:21:49,479 saying like, I want to run this design at 594 00:21:49,480 --> 00:21:50,769 one of the megahertz. 595 00:21:50,770 --> 00:21:52,029 And the worst thing that could happen is 596 00:21:52,030 --> 00:21:53,889 that he sees that he can fit all the 597 00:21:53,890 --> 00:21:56,259 logic into the FPGA, but 598 00:21:56,260 --> 00:21:57,909 the frequency is like ninety five 599 00:21:57,910 --> 00:21:58,929 megahertz. 600 00:21:58,930 --> 00:22:01,119 And so he is like rolling up, 601 00:22:02,410 --> 00:22:04,479 throwing away stuff and putting in you, 602 00:22:05,740 --> 00:22:08,289 trying out new ideas to see 603 00:22:08,290 --> 00:22:09,999 if it fits or not. 604 00:22:10,000 --> 00:22:11,439 And the fun thing about it is that it's 605 00:22:11,440 --> 00:22:13,549 depending on the seat and the seat 606 00:22:13,550 --> 00:22:15,849 sometimes comes, you know, 607 00:22:15,850 --> 00:22:16,809 take some of the fire. 608 00:22:16,810 --> 00:22:19,119 And so sometimes if you are generating 609 00:22:19,120 --> 00:22:21,099 a fire and you're changing the dates in 610 00:22:21,100 --> 00:22:22,629 the Commons, then you will get a 611 00:22:22,630 --> 00:22:24,420 different place and wrote result. 612 00:22:26,050 --> 00:22:28,149 And so there was there was a case where 613 00:22:28,150 --> 00:22:30,279 there wasn't one window said, 614 00:22:30,280 --> 00:22:31,719 Oh, wait, this is the version that we 615 00:22:31,720 --> 00:22:33,819 created on the 26th looks the 616 00:22:33,820 --> 00:22:35,889 best because the Commons was the 617 00:22:35,890 --> 00:22:38,019 right and the IS kicks him to the 618 00:22:38,020 --> 00:22:40,029 best seat versus other than the best 619 00:22:40,030 --> 00:22:41,379 place in road. 620 00:22:41,380 --> 00:22:42,380 And 621 00:22:43,780 --> 00:22:45,849 yeah, so after that, you you have 622 00:22:45,850 --> 00:22:48,759 a configuration file and 623 00:22:48,760 --> 00:22:50,889 this is so you realize that this 624 00:22:50,890 --> 00:22:52,659 is not called an executable because it's 625 00:22:52,660 --> 00:22:54,939 not. It's configuring 626 00:22:54,940 --> 00:22:57,669 the resources within the FPGA 627 00:22:57,670 --> 00:22:59,799 to to do whatever you told 628 00:22:59,800 --> 00:23:02,009 them to do or do something entirely else. 629 00:23:02,010 --> 00:23:04,329 If you have a tiny mistake in your 630 00:23:04,330 --> 00:23:05,330 description language, 631 00:23:06,490 --> 00:23:08,979 by the way, and what you simulate 632 00:23:08,980 --> 00:23:11,019 is what you get, which is not true for 633 00:23:11,020 --> 00:23:13,179 video or very look, if 634 00:23:13,180 --> 00:23:14,229 you're running, if you're running 635 00:23:14,230 --> 00:23:16,239 simulation on when you log a video, it 636 00:23:16,240 --> 00:23:17,709 might be what you're getting at hardware, 637 00:23:17,710 --> 00:23:18,710 but it might be not. 638 00:23:22,990 --> 00:23:25,449 So one of the cool features of 639 00:23:25,450 --> 00:23:27,639 of of refugees is pipeline. 640 00:23:28,660 --> 00:23:30,039 For something you want to multiply, you 641 00:23:30,040 --> 00:23:32,229 want to calculate A-plus B times 642 00:23:32,230 --> 00:23:33,999 C plus de plus 10. 643 00:23:34,000 --> 00:23:36,069 And what you can do is your you have 644 00:23:36,070 --> 00:23:38,839 your inputs ABCD and 645 00:23:38,840 --> 00:23:41,829 you put them into the pipeline 646 00:23:41,830 --> 00:23:44,379 and every clock the data gets processed. 647 00:23:44,380 --> 00:23:46,959 You can see that the green blob 648 00:23:46,960 --> 00:23:49,629 is first computing A-plus B and C plus D, 649 00:23:49,630 --> 00:23:51,759 which is then used as 650 00:23:51,760 --> 00:23:54,339 input for the multiply, 651 00:23:54,340 --> 00:23:55,389 which is then added to 10. 652 00:23:55,390 --> 00:23:57,729 And then you have a results 653 00:23:57,730 --> 00:23:59,809 and every clock you get 654 00:23:59,810 --> 00:24:00,810 the new results. 655 00:24:02,620 --> 00:24:03,909 This is very important to understand 656 00:24:03,910 --> 00:24:06,459 because this is how 657 00:24:06,460 --> 00:24:08,409 refugees are getting there. 658 00:24:08,410 --> 00:24:10,689 I can actually kick kick ass 659 00:24:10,690 --> 00:24:12,669 regarding what I suppose. 660 00:24:14,410 --> 00:24:16,779 So yeah, after just 661 00:24:16,780 --> 00:24:18,879 four cycles or wait, 662 00:24:18,880 --> 00:24:20,859 it was more seven seven cycles. 663 00:24:20,860 --> 00:24:23,289 You have you have all your computer 664 00:24:23,290 --> 00:24:24,939 or your results. 665 00:24:24,940 --> 00:24:25,960 And, you know, 666 00:24:28,510 --> 00:24:31,479 another very cool feature of of Jesus 667 00:24:31,480 --> 00:24:33,009 high speed. I was I was talking about 668 00:24:33,010 --> 00:24:35,169 those you have tons 669 00:24:35,170 --> 00:24:37,509 of GPA or every pin that you have on FPGA 670 00:24:37,510 --> 00:24:39,969 can run you odds and SBI 671 00:24:39,970 --> 00:24:41,829 bus or it is good. 672 00:24:41,830 --> 00:24:43,359 You know, I trust Grant, 673 00:24:44,890 --> 00:24:45,890 you know what I mean. 674 00:24:47,050 --> 00:24:48,549 And the other stuff, every protocol that 675 00:24:48,550 --> 00:24:50,409 you can imagine, most of the protocols 676 00:24:50,410 --> 00:24:52,479 that you can imagine can run on every 677 00:24:52,480 --> 00:24:54,309 pin that you have. 678 00:24:54,310 --> 00:24:56,379 And those pins are actually pretty 679 00:24:56,380 --> 00:24:58,509 fast. So you can have you have shift 680 00:24:58,510 --> 00:25:01,059 the distance within the FPGA 681 00:25:01,060 --> 00:25:03,459 for the inputs so that you can have like 682 00:25:03,460 --> 00:25:06,909 up to 480 or eight megabits 683 00:25:06,910 --> 00:25:09,879 on each pin as input. 684 00:25:09,880 --> 00:25:12,099 And then there are dedicated high speed 685 00:25:12,100 --> 00:25:14,499 receivers where you 686 00:25:14,500 --> 00:25:16,689 can have up to 25 gigabits per second 687 00:25:16,690 --> 00:25:18,879 on one pin or two pins actually 688 00:25:18,880 --> 00:25:19,880 differential. 689 00:25:22,150 --> 00:25:24,519 So this is pretty neat, and we also have 690 00:25:24,520 --> 00:25:26,919 very precise control of the 691 00:25:26,920 --> 00:25:28,389 of the signal. So you can, for example, 692 00:25:28,390 --> 00:25:30,479 say, OK, I want this to be this pin to be 693 00:25:30,480 --> 00:25:32,589 a 3.3 ruled on this one to be one 694 00:25:32,590 --> 00:25:33,579 point eight world. 695 00:25:33,580 --> 00:25:34,869 And you can say there should be a pull 696 00:25:34,870 --> 00:25:36,189 up, there should be a pull down. 697 00:25:36,190 --> 00:25:38,169 And you can also say that the tri 698 00:25:38,170 --> 00:25:40,449 strength which is used for for 699 00:25:40,450 --> 00:25:42,219 creating the edge should be like, you 700 00:25:42,220 --> 00:25:44,469 know, not so high, like one mega a 701 00:25:44,470 --> 00:25:46,429 million pair or like eight million. 702 00:25:46,430 --> 00:25:48,819 So you can really define 703 00:25:48,820 --> 00:25:50,349 how you want the signal to be 704 00:25:52,270 --> 00:25:54,369 and to know we're going to 705 00:25:54,370 --> 00:25:56,619 going to compare superuser. 706 00:25:56,620 --> 00:25:58,929 Refugees are actually the 707 00:25:58,930 --> 00:26:00,339 combination of them. 708 00:26:00,340 --> 00:26:02,919 So sippers are good at 709 00:26:02,920 --> 00:26:04,329 things that you do just once. 710 00:26:04,330 --> 00:26:05,919 You know, if you have if you have a large 711 00:26:05,920 --> 00:26:08,679 piece of code and are just run once, 712 00:26:08,680 --> 00:26:10,779 then it would be very it would be a 713 00:26:10,780 --> 00:26:13,089 huge waste of resources to put that onto 714 00:26:13,090 --> 00:26:14,119 an FPGA. 715 00:26:14,120 --> 00:26:15,819 Refugees are good at things that repeat 716 00:26:15,820 --> 00:26:17,379 very often. 717 00:26:17,380 --> 00:26:19,479 Um yeah, a large complex that you 718 00:26:19,480 --> 00:26:21,819 don't want to implement something like 719 00:26:21,820 --> 00:26:24,189 an operating system on a refugee, 720 00:26:24,190 --> 00:26:25,209 even though it would be really 721 00:26:25,210 --> 00:26:27,519 appreciated to see that if someone 722 00:26:27,520 --> 00:26:30,159 is really masochistic in its nature, then 723 00:26:30,160 --> 00:26:31,720 you can contact me and I will help them 724 00:26:33,010 --> 00:26:34,010 to suffer. 725 00:26:36,120 --> 00:26:37,199 With no 726 00:26:38,800 --> 00:26:40,049 conflict, with the kicking. 727 00:26:41,520 --> 00:26:42,869 I was not at the King Beach 728 00:26:44,460 --> 00:26:45,460 thing yet, 729 00:26:46,920 --> 00:26:49,019 so severe results are 730 00:26:49,020 --> 00:26:51,149 very good for for giving a 731 00:26:51,150 --> 00:26:53,249 quick shot. You know, you're you're 732 00:26:53,250 --> 00:26:55,289 used to fast compile times, it doesn't 733 00:26:55,290 --> 00:26:57,540 take weeks, you know, just like minutes 734 00:26:58,650 --> 00:27:00,809 and you can put it on to 735 00:27:00,810 --> 00:27:01,799 under your recipe. 736 00:27:01,800 --> 00:27:04,049 You do test those works. 737 00:27:04,050 --> 00:27:05,729 What doesn't work? You have very quick 738 00:27:05,730 --> 00:27:07,169 development cycles. 739 00:27:07,170 --> 00:27:09,329 Those are not very common in FPGA 740 00:27:09,330 --> 00:27:10,330 development, 741 00:27:11,490 --> 00:27:13,649 at least until the until the PS Show 742 00:27:13,650 --> 00:27:14,650 takes over the world. 743 00:27:16,290 --> 00:27:18,479 But you can actually combine those 744 00:27:18,480 --> 00:27:19,480 powers so 745 00:27:20,580 --> 00:27:22,649 you can be very good at as, for 746 00:27:22,650 --> 00:27:24,359 example, reprising the metrics tech so 747 00:27:24,360 --> 00:27:25,360 that you can have 748 00:27:26,470 --> 00:27:27,959 it. For example, this if you can run 749 00:27:27,960 --> 00:27:30,299 Linux and exhibits some interesting 750 00:27:30,300 --> 00:27:31,529 data via, isn't it? 751 00:27:31,530 --> 00:27:33,089 And then you feed the data into the 752 00:27:33,090 --> 00:27:35,159 fabric of the FPGA and 753 00:27:35,160 --> 00:27:36,989 you do something interesting with. 754 00:27:36,990 --> 00:27:39,269 So the combination of those boats, this 755 00:27:39,270 --> 00:27:41,699 is a really powerful combination. 756 00:27:41,700 --> 00:27:44,369 And you can also realize 757 00:27:44,370 --> 00:27:46,079 the CPU in the fabric itself. 758 00:27:46,080 --> 00:27:47,789 But the frequencies that you are getting 759 00:27:47,790 --> 00:27:50,069 are like one and that megahertz 760 00:27:50,070 --> 00:27:52,409 were not 50 megahertz, sometimes 761 00:27:52,410 --> 00:27:55,349 200 megahertz, which is on the very new 762 00:27:55,350 --> 00:27:57,719 devices. But you will not get lucky goods 763 00:27:57,720 --> 00:27:59,789 right now, at least because 764 00:27:59,790 --> 00:28:01,170 the good news the good news is that 765 00:28:02,220 --> 00:28:03,879 unlike with superiors where the frequency 766 00:28:03,880 --> 00:28:06,059 you kind of stopped to increase 767 00:28:06,060 --> 00:28:08,189 at two point six gigahertz or 768 00:28:08,190 --> 00:28:10,499 whatever your i7 is right 769 00:28:10,500 --> 00:28:13,859 running right now, you're also 770 00:28:13,860 --> 00:28:17,249 in the FPGA domain and 771 00:28:17,250 --> 00:28:18,989 they are benefiting from the shrinking of 772 00:28:18,990 --> 00:28:21,269 the process so much that the frequencies 773 00:28:21,270 --> 00:28:23,219 are getting very close to one gigahertz 774 00:28:23,220 --> 00:28:25,739 right now in the very, very latest 775 00:28:25,740 --> 00:28:28,469 or just announced version. 776 00:28:28,470 --> 00:28:31,039 And you can also have a sip you realized, 777 00:28:31,040 --> 00:28:33,449 and in the FPGA 778 00:28:33,450 --> 00:28:35,609 itself, those running 779 00:28:35,610 --> 00:28:37,569 at 400 gigahertz or something. 780 00:28:40,530 --> 00:28:42,119 Yeah, so you can. What you can do is you 781 00:28:42,120 --> 00:28:44,909 can accelerate a part of your application 782 00:28:44,910 --> 00:28:47,099 and you can start with a with 783 00:28:47,100 --> 00:28:48,899 a full software implementation that you 784 00:28:48,900 --> 00:28:51,349 run on a sip view and then you just 785 00:28:51,350 --> 00:28:53,009 identify which part is taking a long 786 00:28:53,010 --> 00:28:55,829 time. For example, the cipher 787 00:28:55,830 --> 00:28:57,479 for encrypting something is taking a long 788 00:28:57,480 --> 00:28:59,429 time. And then you just put it into the 789 00:28:59,430 --> 00:29:01,499 fabric and 790 00:29:01,500 --> 00:29:04,049 then you can accelerate things. 791 00:29:04,050 --> 00:29:06,899 I'm going to show you an example very, 792 00:29:06,900 --> 00:29:09,239 very quickly. FPGA that is running at 200 793 00:29:09,240 --> 00:29:11,279 megahertz can beat an i7 794 00:29:13,200 --> 00:29:15,319 right now. And this 795 00:29:15,320 --> 00:29:17,369 is something our diploma rate was about. 796 00:29:17,370 --> 00:29:19,439 This is about the discrete racial 797 00:29:19,440 --> 00:29:21,479 transformation that is used in JPEG 2000, 798 00:29:21,480 --> 00:29:23,159 which is a pretty neat compression 799 00:29:23,160 --> 00:29:24,149 algorithm. 800 00:29:24,150 --> 00:29:26,009 And the way it works is that you have a 801 00:29:26,010 --> 00:29:28,619 2D bracelet that is applied 802 00:29:28,620 --> 00:29:30,059 to rows and then to 803 00:29:31,310 --> 00:29:32,519 to vertical. 804 00:29:32,520 --> 00:29:34,679 And if you look at it and 805 00:29:34,680 --> 00:29:37,079 the see you when you're 806 00:29:37,080 --> 00:29:39,209 this looks like this, there's at 807 00:29:39,210 --> 00:29:41,819 the top, you see the the input pixel 808 00:29:41,820 --> 00:29:43,949 and then they are like combined 809 00:29:43,950 --> 00:29:46,200 into and through other 810 00:29:47,220 --> 00:29:48,839 parts. And then at the end you get to 811 00:29:48,840 --> 00:29:50,969 make one Pixel one or actually you get 812 00:29:50,970 --> 00:29:51,970 two pixels or 813 00:29:54,150 --> 00:29:56,279 so on the CPU when you when you 814 00:29:56,280 --> 00:29:57,280 load the first pixel. 815 00:29:58,740 --> 00:30:00,899 It's a Cashman's and it has to go 816 00:30:00,900 --> 00:30:02,909 to zero noted. 817 00:30:02,910 --> 00:30:04,289 But there is a brief edge. 818 00:30:04,290 --> 00:30:06,479 And so when the next pixel is as 819 00:30:06,480 --> 00:30:08,669 loaded and put through the process, 820 00:30:08,670 --> 00:30:11,489 you get a very efficient process. 821 00:30:11,490 --> 00:30:13,259 So this discrete racial transformation is 822 00:30:13,260 --> 00:30:15,329 basically memory bond. 823 00:30:15,330 --> 00:30:16,889 The computations that you see at the 824 00:30:16,890 --> 00:30:19,079 bottom, they like, they don't contribute 825 00:30:19,080 --> 00:30:21,209 much to the to the to the time that 826 00:30:21,210 --> 00:30:22,320 it takes for them to do 827 00:30:23,340 --> 00:30:24,659 so. 828 00:30:24,660 --> 00:30:26,729 Yeah, if you do it horizontally, you 829 00:30:26,730 --> 00:30:29,129 are your pixels are all in line. 830 00:30:29,130 --> 00:30:30,129 Everything is perfect. 831 00:30:30,130 --> 00:30:32,279 You have preferred cache 832 00:30:32,280 --> 00:30:33,989 is working as expected. 833 00:30:33,990 --> 00:30:36,269 But the problem arises when 834 00:30:36,270 --> 00:30:37,409 when you're actually trying to do the 835 00:30:37,410 --> 00:30:39,479 vertical thing, you 836 00:30:39,480 --> 00:30:41,729 start to add memory address zero and 837 00:30:41,730 --> 00:30:44,579 the next row in a twenty 838 00:30:44,580 --> 00:30:47,879 one thousand one 1024 839 00:30:47,880 --> 00:30:50,189 pixel is at one thousand 840 00:30:50,190 --> 00:30:51,209 twenty four. 841 00:30:51,210 --> 00:30:52,529 And so you have a Cashman's and the 842 00:30:52,530 --> 00:30:54,659 Cashman's and the Cashman's, 843 00:30:54,660 --> 00:30:56,819 and so you have Cashman's. 844 00:30:56,820 --> 00:30:59,639 After Cashman's and 845 00:30:59,640 --> 00:31:02,339 your process, your siptu gets 846 00:31:02,340 --> 00:31:05,279 starts to become really, really slow, 847 00:31:05,280 --> 00:31:07,529 like like a factor of 848 00:31:07,530 --> 00:31:08,999 of 30 or 40. 849 00:31:09,000 --> 00:31:10,589 If you're if you have bad luck 850 00:31:11,760 --> 00:31:12,760 and 851 00:31:13,980 --> 00:31:17,009 it is in an FPGA, what you could do is 852 00:31:17,010 --> 00:31:19,079 you do the horizontal DVT 853 00:31:19,080 --> 00:31:21,299 Jupiter, you put it in your horizontal 854 00:31:21,300 --> 00:31:23,789 pixel and then you store 855 00:31:23,790 --> 00:31:26,129 the results of the 856 00:31:26,130 --> 00:31:28,929 of the horizontal waislitz 857 00:31:28,930 --> 00:31:31,349 in the block around that is in the FPGA 858 00:31:31,350 --> 00:31:34,009 itself. And then you feed it into the. 859 00:31:34,010 --> 00:31:36,199 Intrusive was not the logical 860 00:31:36,200 --> 00:31:37,609 way for the transformation, so it doesn't 861 00:31:37,610 --> 00:31:40,459 go back to the original 862 00:31:40,460 --> 00:31:42,769 DDR external memory, but it's 863 00:31:42,770 --> 00:31:45,139 contained within the FPGA 864 00:31:45,140 --> 00:31:47,299 and those are running at full speed 865 00:31:49,460 --> 00:31:50,779 of your of your fabric. 866 00:31:50,780 --> 00:31:53,419 And so this way you can 867 00:31:53,420 --> 00:31:55,009 you can improve the performance 868 00:31:55,010 --> 00:31:56,549 significantly. 869 00:31:56,550 --> 00:31:59,419 So if you you have 870 00:31:59,420 --> 00:32:01,479 a horizontal line, you have a perfect 871 00:32:01,480 --> 00:32:03,719 cache. It's due to the brief, 872 00:32:03,720 --> 00:32:05,969 which so this is very fast and 873 00:32:05,970 --> 00:32:07,219 in the vertical. 874 00:32:07,220 --> 00:32:09,139 So now you have cache misses all the 875 00:32:09,140 --> 00:32:11,839 time. So you have a significant slowdown. 876 00:32:11,840 --> 00:32:14,209 But in an FPGA, you you're performing 877 00:32:14,210 --> 00:32:17,209 a linear read of your of your image 878 00:32:17,210 --> 00:32:19,309 and then you do magic 879 00:32:19,310 --> 00:32:21,649 with it and then you'd perform 880 00:32:21,650 --> 00:32:23,509 a linear right on the output. 881 00:32:23,510 --> 00:32:25,639 And so they figure is running 882 00:32:25,640 --> 00:32:27,829 at your full memory speed 883 00:32:28,940 --> 00:32:31,339 while your speed was permanently stalled 884 00:32:31,340 --> 00:32:33,349 by the external memory that it has to 885 00:32:33,350 --> 00:32:34,519 use. 886 00:32:34,520 --> 00:32:36,789 And so this way, the 887 00:32:36,790 --> 00:32:38,869 the the the the reflection summation 888 00:32:38,870 --> 00:32:41,059 on the FPGA that we realize that takes 889 00:32:41,060 --> 00:32:43,879 like 50 milliseconds and 890 00:32:43,880 --> 00:32:46,169 on then on an i7 that takes like 891 00:32:46,170 --> 00:32:48,229 a lot of sudden milliseconds or 892 00:32:48,230 --> 00:32:50,239 something like this, even though it is 893 00:32:50,240 --> 00:32:51,859 running at two hundred megahertz while 894 00:32:51,860 --> 00:32:53,929 the i7 is running at two 895 00:32:53,930 --> 00:32:56,209 point six or even three gigahertz 896 00:32:56,210 --> 00:32:57,210 when it's clocking up. 897 00:32:58,160 --> 00:33:00,439 And so this is our FPGA 898 00:33:00,440 --> 00:33:02,509 is can kick ass versus 899 00:33:02,510 --> 00:33:03,889 chips. 900 00:33:03,890 --> 00:33:05,839 There's also, by the way, I put up the 901 00:33:05,840 --> 00:33:07,249 slides in the speaker. 902 00:33:07,250 --> 00:33:08,480 So if you want to look at the shots 903 00:33:09,830 --> 00:33:11,389 at any point later in time, you will find 904 00:33:11,390 --> 00:33:12,390 it online. 905 00:33:13,460 --> 00:33:15,529 So if you're sitting in your project 906 00:33:15,530 --> 00:33:17,150 and you're like, Oh, what should I use? 907 00:33:18,230 --> 00:33:19,819 You always have some obvious choices, 908 00:33:19,820 --> 00:33:22,099 like you have a regular x86, 909 00:33:22,100 --> 00:33:24,119 which is very nice to program or you have 910 00:33:24,120 --> 00:33:25,909 a chip you, which is very powerful, a 911 00:33:25,910 --> 00:33:28,009 floating point, or you have a DSP, which 912 00:33:28,010 --> 00:33:30,199 is like those, which 913 00:33:30,200 --> 00:33:31,279 is very nice to imagine. 914 00:33:31,280 --> 00:33:32,960 Then you have FPGA, which is very good at 915 00:33:35,180 --> 00:33:38,389 almost everything, but not in programing 916 00:33:38,390 --> 00:33:40,069 and then you have a microcontroller. 917 00:33:40,070 --> 00:33:42,289 And so 918 00:33:42,290 --> 00:33:44,779 this is this shot basically is 919 00:33:44,780 --> 00:33:46,879 the showing that it's, you 920 00:33:46,880 --> 00:33:48,199 know, for example, if you want to put an 921 00:33:48,200 --> 00:33:50,419 x86 on your on your quadcopter for 922 00:33:50,420 --> 00:33:53,029 doing something fancy, you know, 923 00:33:53,030 --> 00:33:55,099 you may have you may have a poor problem 924 00:33:55,100 --> 00:33:57,859 because those are kind of power hungry 925 00:33:57,860 --> 00:33:59,989 and embedding x86 926 00:33:59,990 --> 00:34:02,779 processors is challenging, 927 00:34:02,780 --> 00:34:04,969 at least. But no, there's a good one, but 928 00:34:04,970 --> 00:34:06,019 computers. 929 00:34:06,020 --> 00:34:08,299 But if you have a 240 world 930 00:34:08,300 --> 00:34:09,709 power cut going down from your 931 00:34:09,710 --> 00:34:10,999 quadcopter, that's not very helpful. 932 00:34:12,920 --> 00:34:14,869 They are very good at a floating point 933 00:34:14,870 --> 00:34:16,399 operations that are obviously integer 934 00:34:16,400 --> 00:34:18,408 operations and control flow stuff. 935 00:34:18,409 --> 00:34:20,738 Control itself is all this was, if else 936 00:34:20,739 --> 00:34:22,489 Ellison break and jump and continue. 937 00:34:24,139 --> 00:34:26,238 They it is very hard to 938 00:34:26,239 --> 00:34:28,850 get a GPA all attached to an x86. 939 00:34:29,929 --> 00:34:31,130 So this is no fun 940 00:34:32,510 --> 00:34:34,849 and they can't do a pipeline as FPGA 941 00:34:34,850 --> 00:34:35,850 is can do. 942 00:34:36,560 --> 00:34:38,329 But the upside is they are very easy to 943 00:34:38,330 --> 00:34:40,189 program and they are very easily 944 00:34:40,190 --> 00:34:41,238 available. 945 00:34:41,239 --> 00:34:44,419 But if you want to do very precise timing 946 00:34:44,420 --> 00:34:45,769 in the area of nanoseconds of 947 00:34:45,770 --> 00:34:48,709 microseconds, things get very difficult. 948 00:34:48,710 --> 00:34:50,809 The GPUs, you don't want to put those on 949 00:34:50,810 --> 00:34:51,810 the quadcopter. Definitely. 950 00:34:53,690 --> 00:34:55,698 They are very hard to embed and they are 951 00:34:55,699 --> 00:34:57,139 definitely not no low power. 952 00:34:58,190 --> 00:35:00,109 They are very, very, very good at 953 00:35:00,110 --> 00:35:01,819 floating point operations that are taking 954 00:35:01,820 --> 00:35:02,820 that can be paralyzed. 955 00:35:03,730 --> 00:35:04,849 Integer operations as well. 956 00:35:04,850 --> 00:35:05,850 Control flow is like 957 00:35:08,060 --> 00:35:09,860 I always like nonexistence 958 00:35:11,000 --> 00:35:12,559 pipeline and cannot be done. 959 00:35:12,560 --> 00:35:14,529 The probability is like a bit better than 960 00:35:14,530 --> 00:35:15,530 the is, 961 00:35:16,760 --> 00:35:18,829 but worse than the CPU, and you 962 00:35:18,830 --> 00:35:20,449 have absolutely no control of timing. 963 00:35:20,450 --> 00:35:22,579 Whatever these 964 00:35:22,580 --> 00:35:25,009 pieces are, like very powerful for 965 00:35:25,010 --> 00:35:27,049 multiply accumulates applications was for 966 00:35:27,050 --> 00:35:29,149 the rings and all this 967 00:35:29,150 --> 00:35:30,499 stuff. This is what they are optimized 968 00:35:30,500 --> 00:35:31,789 for. They also optimized for being 969 00:35:31,790 --> 00:35:33,859 embedded into into a power 970 00:35:33,860 --> 00:35:35,389 constrained device. 971 00:35:35,390 --> 00:35:37,489 And so, yeah, you can see what 972 00:35:37,490 --> 00:35:38,490 they are good at. 973 00:35:40,670 --> 00:35:42,679 The microcontroller, obviously is at the 974 00:35:42,680 --> 00:35:44,659 very low end like I was thinking about 975 00:35:44,660 --> 00:35:45,619 like a normal. 976 00:35:45,620 --> 00:35:47,239 It doesn't do very floating point 977 00:35:47,240 --> 00:35:49,369 operations and 978 00:35:49,370 --> 00:35:51,019 the infra, just like you can do 979 00:35:51,020 --> 00:35:52,309 everything. 980 00:35:52,310 --> 00:35:54,199 But the problem is that floating point 981 00:35:54,200 --> 00:35:56,209 operations are not well supported in the 982 00:35:56,210 --> 00:35:57,349 latest vendor tools. 983 00:35:57,350 --> 00:35:58,909 They are claiming that they can do 984 00:35:58,910 --> 00:36:00,949 floating points, but they are very 985 00:36:00,950 --> 00:36:03,289 expensive in an area and frequency 986 00:36:03,290 --> 00:36:04,579 perspective. 987 00:36:04,580 --> 00:36:05,779 Control flow is like 988 00:36:07,430 --> 00:36:09,959 not very, quite hard to do. 989 00:36:09,960 --> 00:36:12,079 You have to create state machines. 990 00:36:12,080 --> 00:36:13,519 You know, those ones that you heard about 991 00:36:13,520 --> 00:36:15,499 in your lectures during the university 992 00:36:15,500 --> 00:36:16,549 that you it's not like why? 993 00:36:16,550 --> 00:36:17,930 Why? Why would I ever need that 994 00:36:19,250 --> 00:36:20,329 for programing of projects? 995 00:36:20,330 --> 00:36:21,330 You need those. 996 00:36:22,520 --> 00:36:24,649 But I o 997 00:36:24,650 --> 00:36:25,650 capabilities are like 998 00:36:26,720 --> 00:36:28,069 ginormous. 999 00:36:28,070 --> 00:36:30,559 You know, there is there's a 1000 1000 00:36:30,560 --> 00:36:32,839 pin FPGA that you can buy and 1001 00:36:32,840 --> 00:36:33,979 you have like your. 1002 00:36:33,980 --> 00:36:36,679 Multiple hundreds, like 600 or 700 1003 00:36:36,680 --> 00:36:38,329 general purpose i o that you can use for 1004 00:36:38,330 --> 00:36:40,069 whatever you want to. 1005 00:36:40,070 --> 00:36:42,109 And obviously they can do pipeline, which 1006 00:36:42,110 --> 00:36:43,639 is pretty cool. 1007 00:36:43,640 --> 00:36:46,519 Well, the community is a bit challenging, 1008 00:36:46,520 --> 00:36:48,109 but if you want to do with timing, those 1009 00:36:48,110 --> 00:36:49,429 are really, really good. 1010 00:36:49,430 --> 00:36:51,409 You can you can do a really precise 1011 00:36:51,410 --> 00:36:53,749 timing up to up to a nanosecond 1012 00:36:53,750 --> 00:36:55,819 level if you 1013 00:36:55,820 --> 00:36:57,949 want to do some, if you, 1014 00:36:57,950 --> 00:36:59,509 for example, want to violate the set up 1015 00:36:59,510 --> 00:37:01,639 and whole time of registers. 1016 00:37:01,640 --> 00:37:02,869 You can do it with refugees. 1017 00:37:04,100 --> 00:37:06,199 It's pretty cool. There's also a 1018 00:37:06,200 --> 00:37:07,369 very interesting talk about 1019 00:37:09,050 --> 00:37:11,209 taking risks later. 1020 00:37:11,210 --> 00:37:13,519 It's like twenty one, forty 1021 00:37:13,520 --> 00:37:15,589 five and inside one, 1022 00:37:15,590 --> 00:37:17,179 which is which you should take a look at. 1023 00:37:17,180 --> 00:37:19,249 It's pretty interesting to see. 1024 00:37:19,250 --> 00:37:21,349 Very, very quick overview of what 1025 00:37:21,350 --> 00:37:23,779 the market is so exciting 1026 00:37:23,780 --> 00:37:25,939 in hotel. I like John Dixon and 1027 00:37:25,940 --> 00:37:26,940 Johnson. 1028 00:37:27,650 --> 00:37:29,449 There's really not big of a difference. 1029 00:37:29,450 --> 00:37:31,639 The one is producing in the low power, 1030 00:37:31,640 --> 00:37:33,739 high performance process at TSMC, and the 1031 00:37:33,740 --> 00:37:35,809 other one is probably using 1032 00:37:35,810 --> 00:37:37,339 the high performance, low power process 1033 00:37:37,340 --> 00:37:39,529 of TSMC. And they're fighting each other 1034 00:37:39,530 --> 00:37:41,959 over which one is the better, which is 1035 00:37:41,960 --> 00:37:43,759 which is quite funny to see, but in the 1036 00:37:43,760 --> 00:37:45,049 end, it doesn't really matter which one 1037 00:37:45,050 --> 00:37:46,050 you take. And 1038 00:37:47,270 --> 00:37:49,129 then there is also October, which is no 1039 00:37:49,130 --> 00:37:50,269 my Cosmi. 1040 00:37:50,270 --> 00:37:52,369 Those are, oh, by the way, as exciting as 1041 00:37:52,370 --> 00:37:53,839 the Note 10 Lite, I have like forty five 1042 00:37:53,840 --> 00:37:55,729 percent each share market share each. 1043 00:37:55,730 --> 00:37:56,989 So they are very, very common 1044 00:37:58,010 --> 00:38:00,139 actually are like very low power 1045 00:38:00,140 --> 00:38:02,539 because they are flesh based, unlike 1046 00:38:02,540 --> 00:38:04,849 the exciting ones which are as from 1047 00:38:04,850 --> 00:38:05,850 based. 1048 00:38:07,220 --> 00:38:08,899 There is a the advantage of an Afghan 1049 00:38:08,900 --> 00:38:11,059 flash based one is that you put it on and 1050 00:38:11,060 --> 00:38:13,489 it's there and wire and the S1 based. 1051 00:38:13,490 --> 00:38:16,099 They need to load the configuration from 1052 00:38:16,100 --> 00:38:17,809 an external source before they can pull 1053 00:38:17,810 --> 00:38:19,969 up, which can be a bit challenging when 1054 00:38:19,970 --> 00:38:21,499 you want to do something like PCI 1055 00:38:21,500 --> 00:38:22,500 Express. 1056 00:38:23,120 --> 00:38:25,579 Also, the doctored ones are used 1057 00:38:25,580 --> 00:38:27,949 for space missions and avionics 1058 00:38:27,950 --> 00:38:29,059 and stuff like this. 1059 00:38:29,060 --> 00:38:30,019 So if you wanna do something with 1060 00:38:30,020 --> 00:38:31,549 radiation, I would recommend you to use 1061 00:38:31,550 --> 00:38:32,550 an actor. 1062 00:38:34,430 --> 00:38:35,809 The latest one, I've never used one of 1063 00:38:35,810 --> 00:38:36,810 those. 1064 00:38:37,250 --> 00:38:38,389 They are, they're on the market. 1065 00:38:41,060 --> 00:38:42,409 By the way, if you're if you're 1066 00:38:42,410 --> 00:38:44,479 interested in buying the most expensive 1067 00:38:44,480 --> 00:38:46,579 FPGA, exciting, says 1068 00:38:46,580 --> 00:38:48,769 the one at priced at like 1069 00:38:48,770 --> 00:38:50,539 thirty two thousand euros. 1070 00:38:50,540 --> 00:38:52,609 That is one device, the 1071 00:38:52,610 --> 00:38:54,199 probably the size. 1072 00:38:54,200 --> 00:38:56,379 And but I tell 1073 00:38:56,380 --> 00:38:57,469 I was very close with just 1074 00:38:59,300 --> 00:39:01,099 run about twenty thousand euros, but you 1075 00:39:01,100 --> 00:39:02,100 have to buy three 1076 00:39:03,470 --> 00:39:05,389 so they don't sell this one quantities 1077 00:39:05,390 --> 00:39:07,249 for whatever reason was available. 1078 00:39:08,300 --> 00:39:10,069 I don't think you get free sampling with 1079 00:39:10,070 --> 00:39:11,059 those. 1080 00:39:11,060 --> 00:39:12,060 No. 1081 00:39:15,200 --> 00:39:17,429 If you want to head into programing 1082 00:39:17,430 --> 00:39:18,899 effigies, you're probably thinking, what, 1083 00:39:18,900 --> 00:39:21,119 what, what, what should I buy? 1084 00:39:21,120 --> 00:39:23,879 This list is by far complete. 1085 00:39:23,880 --> 00:39:25,979 It's just just some balls that I 1086 00:39:25,980 --> 00:39:28,019 heard about that I found interesting. 1087 00:39:28,020 --> 00:39:30,179 And the cheap ones are actually quite 1088 00:39:30,180 --> 00:39:31,409 well. 1089 00:39:31,410 --> 00:39:32,789 And the one that you see in the upper 1090 00:39:32,790 --> 00:39:35,489 left corner, which is the shield, what 1091 00:39:35,490 --> 00:39:37,829 I will introduce few that's 1092 00:39:37,830 --> 00:39:39,210 in my little talk. It's a 1093 00:39:40,250 --> 00:39:42,719 21:45 and Hall six. 1094 00:39:42,720 --> 00:39:44,819 I guess this should 1095 00:39:44,820 --> 00:39:45,809 be a really cheap shot. 1096 00:39:45,810 --> 00:39:46,810 I'd like 30 euros 1097 00:39:48,000 --> 00:39:49,650 was certainly something euros 1098 00:39:51,480 --> 00:39:53,729 from the the start 1099 00:39:53,730 --> 00:39:55,679 is a circular system on a chip, which is 1100 00:39:55,680 --> 00:39:57,929 like a CPU and an effigy. 1101 00:39:57,930 --> 00:40:00,179 And those are very interesting balls 1102 00:40:00,180 --> 00:40:02,699 because especially the Demichelis 1103 00:40:02,700 --> 00:40:04,979 that boards, because you have a 1104 00:40:04,980 --> 00:40:08,129 context, a dual core Cortex A9 1105 00:40:08,130 --> 00:40:10,349 Cortex R9 running at one gigahertz, 1106 00:40:10,350 --> 00:40:12,659 where you can run the perfect Linux and 1107 00:40:12,660 --> 00:40:14,819 then you have all the fabric as well. 1108 00:40:14,820 --> 00:40:16,919 So yeah, and the cheapest 1109 00:40:16,920 --> 00:40:18,839 way to buy them is by ordering the 1110 00:40:18,840 --> 00:40:19,909 parallel board. 1111 00:40:19,910 --> 00:40:22,619 But you also have the very strange 1112 00:40:22,620 --> 00:40:24,749 16 core core that 1113 00:40:24,750 --> 00:40:26,099 they are actually trying to sell, but 1114 00:40:26,100 --> 00:40:27,749 only there is some. If there's a single 1115 00:40:27,750 --> 00:40:30,059 FPGA, which is pretty cool and 1116 00:40:30,060 --> 00:40:32,159 the price is unbeatable because they 1117 00:40:32,160 --> 00:40:34,349 are, you're 1118 00:40:34,350 --> 00:40:36,059 putting some money into distributing 1119 00:40:36,060 --> 00:40:37,060 those. 1120 00:40:38,520 --> 00:40:40,139 Yeah, those are. There is a Dalton clock, 1121 00:40:40,140 --> 00:40:42,389 which is which was introduced 1122 00:40:42,390 --> 00:40:44,579 at the second this 1123 00:40:44,580 --> 00:40:47,099 year, which is also an 1124 00:40:47,100 --> 00:40:49,259 actual FPGA with was 1125 00:40:49,260 --> 00:40:51,299 a microcontroller. 1126 00:40:51,300 --> 00:40:53,969 And yeah, so 1127 00:40:53,970 --> 00:40:56,849 if you are interested in getting started, 1128 00:40:56,850 --> 00:40:59,819 programing FPGA is there will also be a 1129 00:40:59,820 --> 00:41:01,829 workshop tomorrow at 9:00 p.m. 1130 00:41:01,830 --> 00:41:03,779 and half. If you can actually try to get 1131 00:41:03,780 --> 00:41:04,780 somebody these blinking, 1132 00:41:05,970 --> 00:41:08,309 please install exciting tools 1133 00:41:08,310 --> 00:41:09,479 beforehand. 1134 00:41:09,480 --> 00:41:11,369 They are six gigabit and download and 1135 00:41:11,370 --> 00:41:13,379 they take 20 gigabyte of your workspace 1136 00:41:13,380 --> 00:41:15,599 off your disk space and they 1137 00:41:15,600 --> 00:41:17,010 almost run on Linux. 1138 00:41:20,220 --> 00:41:21,659 Well, yeah. 1139 00:41:21,660 --> 00:41:22,949 So if you're if you're interested in 1140 00:41:22,950 --> 00:41:24,689 getting some blinking ideas or if you 1141 00:41:24,690 --> 00:41:26,609 want to learn more about the physical 1142 00:41:26,610 --> 00:41:28,349 boards, you can find that there. 1143 00:41:28,350 --> 00:41:29,999 And are there any questions? 1144 00:41:41,830 --> 00:41:43,359 Thank you. If you have questions, please 1145 00:41:43,360 --> 00:41:44,439 line up on the microphones. 1146 00:41:45,550 --> 00:41:47,289 They don't have numbers, but we'll figure 1147 00:41:47,290 --> 00:41:49,029 that out. Do we have any questions from 1148 00:41:49,030 --> 00:41:50,030 the internet? 1149 00:41:53,920 --> 00:41:55,269 Apparently not. 1150 00:41:55,270 --> 00:41:57,909 So let's start with 1151 00:41:57,910 --> 00:41:58,910 what you're out there. 1152 00:41:59,920 --> 00:42:01,359 We were talking about a high level 1153 00:42:01,360 --> 00:42:03,369 synthesis of tools, and you are saying 1154 00:42:03,370 --> 00:42:05,079 that they are actually better, at least 1155 00:42:05,080 --> 00:42:06,099 for the next 10 years. 1156 00:42:06,100 --> 00:42:07,299 Could you go a little bit into the 1157 00:42:07,300 --> 00:42:08,739 experience you have made with them? 1158 00:42:10,360 --> 00:42:13,359 OK, so 1159 00:42:13,360 --> 00:42:14,619 the high level synthesis tools? 1160 00:42:17,050 --> 00:42:18,050 Yeah. 1161 00:42:19,750 --> 00:42:21,609 So there is there are those high level 1162 00:42:21,610 --> 00:42:23,349 tools that are actually generating 1163 00:42:24,550 --> 00:42:26,199 code for you. And they. 1164 00:42:27,520 --> 00:42:29,889 So my experience was I was the latest 1165 00:42:29,890 --> 00:42:32,079 Riverdale's readers would 1166 00:42:32,080 --> 00:42:34,659 just like to see to 1167 00:42:34,660 --> 00:42:36,940 audio tools that sightings of us. 1168 00:42:37,990 --> 00:42:40,089 I wasn't able to get anything useful out 1169 00:42:40,090 --> 00:42:41,090 of it. 1170 00:42:41,680 --> 00:42:44,889 There is also a side to a hot trail from 1171 00:42:44,890 --> 00:42:47,080 from right to human methods, which 1172 00:42:48,430 --> 00:42:51,429 so in general it seemed to echo 1173 00:42:51,430 --> 00:42:53,529 compilers. They work well, for example, 1174 00:42:53,530 --> 00:42:55,110 is that the vendors provided with them. 1175 00:42:56,140 --> 00:42:59,499 I haven't yet seen any 1176 00:42:59,500 --> 00:43:01,479 any Real-World application written with 1177 00:43:01,480 --> 00:43:04,059 it that has a decent performance 1178 00:43:04,060 --> 00:43:06,129 or did anything really 1179 00:43:06,130 --> 00:43:07,130 useful with it. 1180 00:43:07,900 --> 00:43:09,309 The model of similar things. 1181 00:43:09,310 --> 00:43:11,409 The thing is, there's 1182 00:43:11,410 --> 00:43:13,729 a bit better because actually 1183 00:43:13,730 --> 00:43:16,059 exciting are supporting them with with 1184 00:43:16,060 --> 00:43:18,129 blocks and they do some 1185 00:43:18,130 --> 00:43:19,809 neat optimizations. 1186 00:43:19,810 --> 00:43:21,879 So this is the model of something 1187 00:43:21,880 --> 00:43:24,399 I have seen in the wild, 1188 00:43:24,400 --> 00:43:26,379 then used successfully. 1189 00:43:26,380 --> 00:43:27,939 So this is something to look at. 1190 00:43:29,230 --> 00:43:31,289 There's also some open 1191 00:43:31,290 --> 00:43:33,369 source HDR translators that 1192 00:43:33,370 --> 00:43:34,600 are working more or less. 1193 00:43:35,620 --> 00:43:36,620 OK, 1194 00:43:38,860 --> 00:43:40,749 the gentleman in the striped shirt, the 1195 00:43:40,750 --> 00:43:41,750 side. 1196 00:43:42,790 --> 00:43:45,279 Have you ever tried Dmay 1197 00:43:45,280 --> 00:43:47,649 with PCI Express? 1198 00:43:47,650 --> 00:43:49,749 And there 1199 00:43:49,750 --> 00:43:51,819 are examples that 1200 00:43:51,820 --> 00:43:54,039 you could put onto an FPGA, 1201 00:43:54,040 --> 00:43:56,649 but I haven't tried it personally yet. 1202 00:43:56,650 --> 00:43:58,569 OK. But it should be definitely possible. 1203 00:43:58,570 --> 00:43:59,570 Yes. 1204 00:43:59,890 --> 00:44:02,109 And the next thing that you can do is put 1205 00:44:02,110 --> 00:44:05,019 the slide with your bots on it this 1206 00:44:05,020 --> 00:44:06,020 way. 1207 00:44:07,150 --> 00:44:08,529 Yeah, OK. 1208 00:44:08,530 --> 00:44:11,109 That's a box with a CPU and and 1209 00:44:11,110 --> 00:44:13,239 if you use it on. 1210 00:44:17,040 --> 00:44:19,249 Is it possible on 1211 00:44:19,250 --> 00:44:21,369 on which box, which both 1212 00:44:21,370 --> 00:44:23,489 have expressed support? 1213 00:44:24,790 --> 00:44:26,439 None of the votes that I listed here. 1214 00:44:26,440 --> 00:44:27,909 There are plenty of ports with PCI 1215 00:44:27,910 --> 00:44:30,069 Express. They are usually not cheapest 1216 00:44:30,070 --> 00:44:30,969 one. 1217 00:44:30,970 --> 00:44:33,069 I was always aiming for boats that are 1218 00:44:33,070 --> 00:44:34,299 rather affordable. 1219 00:44:34,300 --> 00:44:36,639 Unfortunately, a lot of ports really go 1220 00:44:36,640 --> 00:44:38,739 standard 500 euros, which 1221 00:44:38,740 --> 00:44:40,059 is not something that you want to spend 1222 00:44:40,060 --> 00:44:42,189 if you don't know what you 1223 00:44:42,190 --> 00:44:43,359 should do with it. 1224 00:44:43,360 --> 00:44:45,039 The Pisasale board provides an answer to 1225 00:44:45,040 --> 00:44:46,960 that. Or you can do plinking it with its 1226 00:44:48,670 --> 00:44:49,719 advantages. 1227 00:44:49,720 --> 00:44:50,800 OK, thanks. 1228 00:44:51,910 --> 00:44:53,469 Let's take a question from that line. 1229 00:44:53,470 --> 00:44:55,690 And after that, from over there, 1230 00:44:56,920 --> 00:44:57,549 I'm not actually 1231 00:44:57,550 --> 00:44:59,439 a question. I have a script to build 1232 00:44:59,440 --> 00:45:01,659 Debian packages from the ultra toolchain 1233 00:45:01,660 --> 00:45:02,830 if anyone needs it. 1234 00:45:04,060 --> 00:45:05,060 Oh, that's pretty cool. 1235 00:45:07,690 --> 00:45:09,699 I have a question regarding a specific 1236 00:45:09,700 --> 00:45:11,889 use case, namely 1237 00:45:11,890 --> 00:45:13,389 bitcoin number crunching. 1238 00:45:16,540 --> 00:45:18,669 Are there any like open source 1239 00:45:18,670 --> 00:45:21,009 projects or anything 1240 00:45:21,010 --> 00:45:23,289 like that? And if so, 1241 00:45:23,290 --> 00:45:25,599 how much of resources 1242 00:45:25,600 --> 00:45:27,939 in terms of time and money would 1243 00:45:27,940 --> 00:45:30,399 one have to invest to to get some real 1244 00:45:30,400 --> 00:45:31,400 profit out of it 1245 00:45:32,620 --> 00:45:34,719 for you? I mean, I know it's a very 1246 00:45:34,720 --> 00:45:35,919 specific question, 1247 00:45:35,920 --> 00:45:37,419 but I have a good answer for it. 1248 00:45:37,420 --> 00:45:39,879 So a friend of mine was buying this 1249 00:45:39,880 --> 00:45:42,159 rig of like four bots, 1250 00:45:42,160 --> 00:45:44,769 which is a very big Spartan 1251 00:45:44,770 --> 00:45:47,889 Alex, one of those 50 on them, and 1252 00:45:47,890 --> 00:45:49,119 he was mining some bitcoins. 1253 00:45:49,120 --> 00:45:50,799 With that, there is there are plenty of 1254 00:45:50,800 --> 00:45:52,089 open source projects for it. 1255 00:45:52,090 --> 00:45:54,549 You will find them very easily. 1256 00:45:54,550 --> 00:45:56,649 The problem is that was the latest 1257 00:45:56,650 --> 00:45:58,629 increase in the complexity of the bitcoin 1258 00:45:58,630 --> 00:46:01,149 mining algorithm and the increase of 1259 00:46:01,150 --> 00:46:03,339 of A6 being fairly 1260 00:46:03,340 --> 00:46:04,709 good available. 1261 00:46:04,710 --> 00:46:05,710 The 1262 00:46:06,820 --> 00:46:09,939 it's not not now not longer 1263 00:46:09,940 --> 00:46:12,159 feasible to to use FPGA 1264 00:46:12,160 --> 00:46:13,659 for mining bitcoins in a 1265 00:46:15,310 --> 00:46:17,079 if your mom doesn't pay the electric 1266 00:46:17,080 --> 00:46:18,080 bill. 1267 00:46:26,780 --> 00:46:28,579 Since we have no other people at 1268 00:46:28,580 --> 00:46:30,809 microphones, the 1269 00:46:30,810 --> 00:46:32,239 guys over there just go through it. 1270 00:46:32,240 --> 00:46:34,399 And until then, thanks for thank 1271 00:46:34,400 --> 00:46:36,609 you for your presentation, but you sound 1272 00:46:36,610 --> 00:46:37,789 that. 1273 00:46:37,790 --> 00:46:39,179 Oh geez. 1274 00:46:39,180 --> 00:46:40,759 I'm good at input output. 1275 00:46:40,760 --> 00:46:42,829 And if you come by a speaker 1276 00:46:42,830 --> 00:46:44,959 and if you do that, you will 1277 00:46:44,960 --> 00:46:46,729 get some nice results. 1278 00:46:46,730 --> 00:46:48,889 But actually, there is 1279 00:46:48,890 --> 00:46:51,199 a problem in interfaces between the 1280 00:46:51,200 --> 00:46:53,509 computer and the effigy, 1281 00:46:53,510 --> 00:46:55,379 because if you're having to 1282 00:46:56,450 --> 00:46:58,519 speak on a pig, you 1283 00:46:58,520 --> 00:46:59,479 will have problems. 1284 00:46:59,480 --> 00:47:01,789 If you and if you haven't say express 1285 00:47:01,790 --> 00:47:03,859 on the same board, so you 1286 00:47:03,860 --> 00:47:06,379 are bound to for about 1287 00:47:06,380 --> 00:47:09,529 20 megabits per second 1288 00:47:09,530 --> 00:47:11,659 in transfer and transmission between 1289 00:47:11,660 --> 00:47:12,889 you and f g. 1290 00:47:12,890 --> 00:47:14,690 And where is the profit? 1291 00:47:15,950 --> 00:47:17,809 Well, there are definitely bots available 1292 00:47:17,810 --> 00:47:19,999 where we have DMA address 1293 00:47:20,000 --> 00:47:22,130 access to your through your host 1294 00:47:23,300 --> 00:47:25,369 memory. So if you want, 1295 00:47:25,370 --> 00:47:27,229 if you this is very possible that you put 1296 00:47:27,230 --> 00:47:29,089 your FPGA bought into the PCI Express 1297 00:47:29,090 --> 00:47:30,889 slot and you have to. 1298 00:47:30,890 --> 00:47:33,019 I said if you're currently going to say 1299 00:47:33,020 --> 00:47:35,299 Express, so you know you 1300 00:47:35,300 --> 00:47:36,409 can do nothing. 1301 00:47:36,410 --> 00:47:38,729 Well, you can have PCI Express 1302 00:47:38,730 --> 00:47:40,279 and just not with the bots that I was 1303 00:47:40,280 --> 00:47:42,199 listing here. That was my point. 1304 00:47:42,200 --> 00:47:44,629 And also there is there are 1305 00:47:44,630 --> 00:47:47,089 the if you if you're using this, 1306 00:47:47,090 --> 00:47:49,129 the same process as it's called from some 1307 00:47:49,130 --> 00:47:51,649 savings where you have the CPU within 1308 00:47:51,650 --> 00:47:53,779 the day of the fabric, you 1309 00:47:53,780 --> 00:47:55,879 have a very, very broad access to the 1310 00:47:55,880 --> 00:47:57,319 fabric, obviously. 1311 00:47:57,320 --> 00:47:59,779 And I 1312 00:47:59,780 --> 00:48:01,939 agree talk how 1313 00:48:01,940 --> 00:48:03,769 cheap and small are they going to get 1314 00:48:03,770 --> 00:48:06,109 like thinking you want to reduce 1315 00:48:06,110 --> 00:48:08,269 complex ability on the board and shifted 1316 00:48:08,270 --> 00:48:10,489 towards software, kind of like 1317 00:48:10,490 --> 00:48:12,229 an Arduino where I can put in like, I 1318 00:48:12,230 --> 00:48:14,179 don't know, motor controller FTD and some 1319 00:48:14,180 --> 00:48:16,459 DSP, but I don't want to do that for 50 1320 00:48:16,460 --> 00:48:18,349 quid, right? So how how cheap are they 1321 00:48:18,350 --> 00:48:19,339 going to go? 1322 00:48:19,340 --> 00:48:22,309 Well, the 1323 00:48:22,310 --> 00:48:24,449 on the I think the abuse issue 1324 00:48:24,450 --> 00:48:26,549 that I'm going to to present, 1325 00:48:26,550 --> 00:48:28,849 this is like a very a lower bound 1326 00:48:28,850 --> 00:48:31,009 of what you can have with an FPGA that 1327 00:48:31,010 --> 00:48:33,169 is usable in the in a very 1328 00:48:33,170 --> 00:48:34,519 flexible way. 1329 00:48:34,520 --> 00:48:35,889 You can. 1330 00:48:35,890 --> 00:48:38,329 The FPGA itself costs like eleven 1331 00:48:38,330 --> 00:48:39,949 euros if you buy it single volume. 1332 00:48:41,330 --> 00:48:43,699 Did you? And it's it's fairly 1333 00:48:43,700 --> 00:48:45,409 OK from a size perspective. 1334 00:48:45,410 --> 00:48:47,569 Of course, there are very small FPGA, so 1335 00:48:47,570 --> 00:48:49,819 CPU Aldi's for doing IoT 1336 00:48:49,820 --> 00:48:51,919 stuff like this, and they can go 1337 00:48:51,920 --> 00:48:54,019 down like, you know, two euros, three 1338 00:48:54,020 --> 00:48:55,020 euros. 1339 00:48:55,580 --> 00:48:56,580 Thanks. 1340 00:48:58,650 --> 00:49:00,789 Firstly, just a comment on the 1341 00:49:00,790 --> 00:49:02,460 PCI question, 1342 00:49:03,480 --> 00:49:05,759 the cyclone five certainly is 1343 00:49:05,760 --> 00:49:08,729 available with a hard Peace Corps 1344 00:49:08,730 --> 00:49:10,949 on die and some 1345 00:49:10,950 --> 00:49:12,030 of the terror 1346 00:49:14,910 --> 00:49:17,279 development boards, for that part, have 1347 00:49:17,280 --> 00:49:20,159 PCI on board. 1348 00:49:20,160 --> 00:49:22,409 Yeah. Not cheap, however. 1349 00:49:22,410 --> 00:49:25,409 Yeah, no. The thing is the reason why 1350 00:49:25,410 --> 00:49:27,749 why they have had PCI 1351 00:49:27,750 --> 00:49:29,849 Express courses because 1352 00:49:29,850 --> 00:49:32,009 well, after plugging into the computer, 1353 00:49:32,010 --> 00:49:34,079 they have to respond within within 1354 00:49:34,080 --> 00:49:35,909 one or two milliseconds. 1355 00:49:35,910 --> 00:49:38,189 And usually, if you have a big FPGA, 1356 00:49:38,190 --> 00:49:40,209 the loading the configuration takes 1357 00:49:40,210 --> 00:49:41,369 longer time. 1358 00:49:41,370 --> 00:49:43,589 Then then those one or two milliseconds, 1359 00:49:43,590 --> 00:49:45,929 which which would not allow you to use 1360 00:49:45,930 --> 00:49:48,179 the plug and your FPGA board into 1361 00:49:48,180 --> 00:49:50,639 a regular x86 board. 1362 00:49:50,640 --> 00:49:52,739 And this is why they introduced hardcore 1363 00:49:54,210 --> 00:49:55,210 PCI Express. 1364 00:49:56,400 --> 00:49:58,320 I also wonder about the 1365 00:49:59,940 --> 00:50:02,639 choice to try to develop C2 1366 00:50:02,640 --> 00:50:05,069 to cut its deal 1367 00:50:05,070 --> 00:50:07,709 compilers since C is fundamentally 1368 00:50:07,710 --> 00:50:09,959 sequential, whereas 1369 00:50:09,960 --> 00:50:12,599 instills are fundamentally 1370 00:50:12,600 --> 00:50:14,009 personalized. 1371 00:50:14,010 --> 00:50:15,869 And I just wonder if it's really to 1372 00:50:15,870 --> 00:50:17,579 figure out where we've converging 1373 00:50:17,580 --> 00:50:20,069 functional programing languages 1374 00:50:20,070 --> 00:50:22,229 to there, which 1375 00:50:22,230 --> 00:50:23,849 might be a much better fit. 1376 00:50:23,850 --> 00:50:26,159 Yes, there are some items that 1377 00:50:26,160 --> 00:50:28,199 porting bringing the function of holding 1378 00:50:28,200 --> 00:50:30,389 them to programing 1379 00:50:30,390 --> 00:50:32,969 hardware, but 1380 00:50:32,970 --> 00:50:34,679 it didn't get any traction outside of 1381 00:50:34,680 --> 00:50:36,899 academia, unfortunately. 1382 00:50:36,900 --> 00:50:37,900 Thank you. 1383 00:50:38,280 --> 00:50:39,599 We have a question from the internet. 1384 00:50:42,240 --> 00:50:43,620 One question from the internet. 1385 00:50:45,840 --> 00:50:48,149 Is there Verdon in FPGA is 1386 00:50:48,150 --> 00:50:50,249 as in do they break over time 1387 00:50:50,250 --> 00:50:51,330 and how much time 1388 00:50:54,060 --> 00:50:56,670 I have yet to break an FPGA? 1389 00:50:58,350 --> 00:51:00,659 Well, if you have a flash based 1390 00:51:00,660 --> 00:51:02,759 FPGA, obviously, 1391 00:51:02,760 --> 00:51:04,859 if you have like only a limited 1392 00:51:04,860 --> 00:51:07,259 lifetime of like a million 1393 00:51:07,260 --> 00:51:09,479 years before the 1394 00:51:09,480 --> 00:51:11,549 configuration gets lost and you 1395 00:51:11,550 --> 00:51:13,709 can only configure it like 1396 00:51:13,710 --> 00:51:15,809 a few million 1397 00:51:15,810 --> 00:51:16,810 times or whatever, 1398 00:51:18,330 --> 00:51:20,459 there is no known word on 1399 00:51:20,460 --> 00:51:22,589 that. I am available to be put like 1400 00:51:22,590 --> 00:51:23,590 this. 1401 00:51:26,400 --> 00:51:28,709 And I can I freely choose the 1402 00:51:28,710 --> 00:51:30,959 description I want to use oil, 1403 00:51:30,960 --> 00:51:33,089 bone tools, special tools from the 1404 00:51:33,090 --> 00:51:34,090 windows. 1405 00:51:35,670 --> 00:51:37,769 Let's put it this way most Windows 1406 00:51:37,770 --> 00:51:39,869 supports we 1407 00:51:39,870 --> 00:51:41,489 very look and video 1408 00:51:43,020 --> 00:51:45,119 a little bit different each one so 1409 00:51:45,120 --> 00:51:47,449 that sometimes they're not compatible. 1410 00:51:49,050 --> 00:51:51,119 And what they also 1411 00:51:51,120 --> 00:51:53,339 support is the littlest Edith 1412 00:51:53,340 --> 00:51:55,409 list. So most 1413 00:51:55,410 --> 00:51:58,169 of the tools are in are either generating 1414 00:51:58,170 --> 00:52:00,629 either of those three so that you can use 1415 00:52:00,630 --> 00:52:02,639 them, for example, HD with generating 1416 00:52:02,640 --> 00:52:05,309 video code so that you can use it for 1417 00:52:05,310 --> 00:52:07,019 use with your. It was only when the tool 1418 00:52:07,020 --> 00:52:08,519 that you want to. 1419 00:52:10,010 --> 00:52:12,179 There are any hope for FPGA 1420 00:52:12,180 --> 00:52:14,569 and development boards to drop 1421 00:52:14,570 --> 00:52:16,819 in price towards the microcontroller 1422 00:52:16,820 --> 00:52:19,339 range or is the support for programing 1423 00:52:19,340 --> 00:52:20,340 too complex? 1424 00:52:23,120 --> 00:52:25,549 Let's put it this way on my 1425 00:52:25,550 --> 00:52:27,399 piece actually what there is, there's an 1426 00:52:27,400 --> 00:52:29,539 exciting which is which is 1427 00:52:29,540 --> 00:52:30,540 programing the 1428 00:52:31,880 --> 00:52:34,519 the the FPGA. 1429 00:52:34,520 --> 00:52:36,530 And so I think 1430 00:52:37,670 --> 00:52:39,379 there are some lower bounds if you don't 1431 00:52:39,380 --> 00:52:41,150 want to be subsidized by the vendor. 1432 00:52:43,340 --> 00:52:46,279 I think really that 30 years, this 1433 00:52:46,280 --> 00:52:48,649 is a very lower bound of 1434 00:52:48,650 --> 00:52:51,829 what you can. You can create a 1435 00:52:51,830 --> 00:52:54,529 board that is interesting 1436 00:52:54,530 --> 00:52:56,629 for and can has a FPGA 1437 00:52:56,630 --> 00:52:58,839 that does something interesting. 1438 00:52:58,840 --> 00:53:01,249 So I don't think 1439 00:53:01,250 --> 00:53:03,589 that it will ever be suitable 1440 00:53:03,590 --> 00:53:04,699 to say, oh no. 1441 00:53:04,700 --> 00:53:06,799 Instead of using a that more, 1442 00:53:06,800 --> 00:53:08,510 I will use an FPGA. 1443 00:53:13,170 --> 00:53:15,439 Is it possible to record the 1444 00:53:15,440 --> 00:53:17,849 the landfills at one time 1445 00:53:17,850 --> 00:53:19,979 so their records of the threat of so 1446 00:53:19,980 --> 00:53:21,209 what do you find FPGA 1447 00:53:22,320 --> 00:53:23,249 eve? 1448 00:53:23,250 --> 00:53:25,440 Well, if you if you ask the vendors, yes, 1449 00:53:26,490 --> 00:53:28,139 if you try it in practice, it's like, 1450 00:53:28,140 --> 00:53:29,250 Well, I know 1451 00:53:30,840 --> 00:53:32,579 it's in theory it's possible to 1452 00:53:32,580 --> 00:53:33,779 reconfigure the FPGA. 1453 00:53:33,780 --> 00:53:34,780 Why did this running? 1454 00:53:35,880 --> 00:53:37,559 I was talking with some winners and they 1455 00:53:37,560 --> 00:53:39,659 said, OK, but it's not like you can 1456 00:53:39,660 --> 00:53:40,889 change the configuration like every 1457 00:53:40,890 --> 00:53:42,179 millisecond, which would be really 1458 00:53:42,180 --> 00:53:43,679 interesting and awesome. 1459 00:53:43,680 --> 00:53:45,569 But it's more like, you know, they are 1460 00:53:45,570 --> 00:53:47,819 like, you can have a change 1461 00:53:47,820 --> 00:53:50,969 of like one time in a minute or so. 1462 00:53:50,970 --> 00:53:52,530 So whatever it takes one minute 1463 00:53:53,790 --> 00:53:55,080 and you have to 1464 00:53:56,340 --> 00:53:59,549 configure and take some time and 1465 00:53:59,550 --> 00:54:01,619 it takes like Figure four J. 1466 00:54:01,620 --> 00:54:03,989 It can it can take like one 1467 00:54:03,990 --> 00:54:05,880 or two seconds and 1468 00:54:07,240 --> 00:54:08,909 you need it to. 1469 00:54:08,910 --> 00:54:10,799 You need to have time to compensate for 1470 00:54:10,800 --> 00:54:11,800 that. 1471 00:54:12,390 --> 00:54:14,669 So, yeah, so in theory, they are. 1472 00:54:14,670 --> 00:54:17,879 You can do that and practice. 1473 00:54:17,880 --> 00:54:20,249 I haven't seen it yet in a practical 1474 00:54:20,250 --> 00:54:22,349 application outside of a window 1475 00:54:22,350 --> 00:54:23,350 demonstration. 1476 00:54:24,760 --> 00:54:26,879 And do 1477 00:54:26,880 --> 00:54:28,290 we have any more internet questions 1478 00:54:31,470 --> 00:54:32,789 in that case? We are done. 1479 00:54:32,790 --> 00:54:34,380 And please thank the speaker again.