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So it's my very great
pleasure to introduce to you, Clifford,
who's going to talk about
a very complex topic I know very
little about, but that's probably going
to change now.
And so please give a warm round of
applause for free and open source.
Very luck to bitstream flow for 40
FPGA.
Thank you,
so I'm talking about the free and open
source, I look kids as far as 45
pages and in particular,
that means I'm going to talk about three
projects because these
three projects together form
this free and open source where
I look to bitstream floor for
this kind of pages.
And the project I'm going to talk about
Project István and project
based is an effort to
reverse engineer and document
the bitstream format for 40
FPGA.
And in particular right
now we support the H, x1, K
and Ajax 8-K.
FPGA is in
theory, we should only also support the
LP one K and LP
8-K if there is such
a one. I don't know FJC
because they just have different
timings, but the piston format is
absolutely identical.
So from the Ice Storm project
we get the documentation
for the documentation
as well as in human readable form
as well as in machine readable form.
So we can write other tools
that to them useful things
with this kind of devices.
And also from project system.
We have a couple of tools that you can
use to read bitstream
files for those FPGA and
convert those bitstream for
our files into different formats
and vice versa.
The second project I'm going to talk
about this, Arachne, an hour
and a half R hours, a place untruthfully
for the ice.
Forty features, and
it's based on the ice storm
documentation.
So I wrote the ice storm documentation
and then I was lucky enough to
find someone
else's name to write
this our place and wrote to
based on the
documentation I wrote.
The third project I'm going to
talk about is users and
users, actually is my kind of
main project that I'm working
on now for a little bit over three years.
And Yosses uses
a huge project, but
simply said it's a very long synthesis
suite. So when you have hardware
designs that are written in Vallelonga
can use users to synthesize
those designs to Netlist for
a variety of different architectures.
And one of those architectures is the ICE
40 FPGA architecture.
But I also have support for
other FPGA series as they have
support for async synthesis and they also
support various formal verification
flows in users and can
talk about this a little bit.
Not very much. Just just a little bit.
And last but not least, I'm going to talk
about the Ichabod, the
Ichabod and Development
Part featuring the 40
features, and
I'm also showing you a little demo, and
that's this contraption here.
We are going to
use this at the end of the talk.
So this is the floor,
the big overview for the floor,
you see, you
start with the sources
and the synthesis script.
Usually the synthesis script just reads
the very log files and then executes
a few macro commands that do everything
that is necessary to synthesize
for the specified target.
And of course, we are looking at this
for the FPGA here in particular,
the output of of users in
this case is a file
is a very easy a very
simple Netlist format.
And it's one of many format that the user
supports as a spec.
And we we've
made some extensions to the play file
format to enable
the use of additional attributes
on sales and parameters, which is
quite useful when you do, for example,
FPGA synthesis and would like
to have like the load configuration
as part of a
instantiation was a
kind of parameter.
Then we take this Netlist and the cliff
file and we pass it on
to Arachne Pinata
Place and vowed to return the composite
and the OZEKI for a of
additional files.
Namely, we give it the physical
constraints file that specifies
where each pin should go
on the Web.
Each input output of the design should
should go on the device to which it
should map.
You can also specify a
script that tells Arachne
what what strategy to
follow and what what of its
internal passes it to execute
and what order.
The output of that is what I call
an ice storm text file.
This is already a very, very
low level file format.
We will see a short example of that
where you can see for
each individual tile just
asks you a block of zeros and ones
and then, you know, OK, in line eight
and column 13
is a bit that has this or that function.
And lastly, we we passed
this István text file to icepack
and icepack is a very simple tool that
can convert this easy to
read text file into
the binary representation that
must be passed to the FPGA in order to
use this design.
Yeah, so let's look at the
first of those four
project that the first part
of Matak project is done.
First, I think I should give you a little
overview of the E40 FPGA
series, because the eyes for the face
are not very
widely used.
I mean, a lot of people use these devices
or quiara devices, but let
I sort of kind of
kind of niche.
So it's a family of small
FPGA, is the largest one,
has a little bit under 8000
lots and lots of
small for input.
Lots of the FPGA
itself is, of course, a kind of grid
of tiles and the different kind of tiles.
There are logic tiles and those logic
tiles have have eight lookup
tables. And for each of those lookup
tables and optional flip flop and
a carry chain logic
that you can use optionally,
there are also some tiles for four block
memory.
They are always coming past.
There's always Ramsbottom
tile in the top tile
and a bottom tile in the top tile.
Together they form
a four kilobyte astron.
And of course there are all tiles
on the edges of
of the scripts that connect
to the programable eye opens, but
also provide the infrastructure necessary
to connect the
FPGA logic with other resources
on the chip like Nelsonville overnight.
A nice thing about
ICE 40 is that they come in quite
reasonable packages, so then you would
like to make your own boards that
can be quite a hassle to work with
biodegrades arrays and stuff like that.
But the ICE 40 features
come in in packages like
144 PIN tulku.
Of that, you can even fold
up a hand if you have to.
And all of them are very cheap
development boards available from Lettice
directly for for this kind of FPGA.
The lettuce I stick cost
less than twenty five dollars.
So it's really affordable for
someone who just would like to
experiment with it and have a quick go
at it.
Also, if you would like to do some
low level stuff and are afraid of
maybe breaking your dashboard by
by fiddling with the configuration, it's
manually, then it's
quite nice to have that part in this
price range.
Nothing is.
Yeah, Americans can simply replace
it.
So in summary, the FBI looks a little
bit like that. We have this, this,
this this group of of of
these program logic blocks.
This are the logic tiles.
We have some some memory tiles that span
two rows.
And you have to add all wall tiles
on the on the edges.
And then in the middle of that slide, we
have a more detailed look into one
of these logic tiles
where we see you have these eight
flip flops, eight
Khari chain elements
and eight lookup tables.
This is also blowing up here
so they can see it in more detail.
However, this is still just
it's still missing stuff.
For example, there is a connection that
goes directly from one output
to the second
input of the next
look and look at people in this chain
bypassing the flip flop.
Yeah, and the bottom right, you see, this
is the spot that you can buy from
that is for under twenty five
dollars, I think it costs twenty five
dollars from let's put it on the twenty
five dollars.
Good service project, Ice Time, we
had a detailed look at this FPGA
sound, we documented
the bitstream format and we wrote
this low level tools that can be used to
work with the streams.
And we also defined a very simple text
file that can be used to just
specify each and every individual
bit in the configuration.
And on the right on this slide, you see a
little excerpt of what this
text file looked like.
So you have your logic
Title nine nine.
And these are, of course, the
coordinates. And then you just have this
this block of ones
and zeros. And then you can when you
when you look up the documentation online
that we provided and you can
decipher that and say, OK, this
is set because it has this function at
this kind of makes sense for what this
configuration does.
So with the tools we can
convert between the text files and the
binary files, and
we can also do a lot of other interesting
stuff, for example, you can take one of
those text files and convert it back
into a behavioral model.
And actually, when I released this
feature the first time, I got quite some
hate mail from people who thought I want
to steal their IP or something.
You can also create timing Netlist
from this bitstream directly.
However, this is under construction,
it's almost done, but not
quite yet.
The reason why we are doing things like
that always on this low level
bitstream format is because
we can create these files from our own
floor, but they can also created for
the bitstream files generated
by letters flow.
So it's very easy to verify
if our interpretation of the
of the bitstream is correct or just
create random badenoch designs
passing through the letters flow, then
convert the output back into something
that is behaviorally analog and then use
something like the formal verification
features in users to check.
If we started with
a.. Figured out at the end a formally
equivalent.
So you can
go to the latest ice storm and
browse the documentation.
I wrote a little
bit of warning here, and
it's a reference that not it's not like
an introductory textbook.
So if you don't
know anything about how FPGA is working
internally, it might be a
hard read,
although it's actually not very well
structured, unfortunately.
But it's not very long.
It's just a few pages of my
recommendation. If you really would like
to know how this FPGA spoke
and what the individual bit means is
to just read the entire thing once and
then you have an overview
of what is.
And for example, most of the
interconnectedness explains in the on
the page for the logic types and
things like like listen to your Burnetts
explained on the on the page to
cover the details.
But it's really small and you can can
read it in maybe an hour or two.
So it's, I think, not so bad.
So the things provided by
my project besides the
the actual tools, the documentation
provided, this is a written
documentation that gives you an overview.
Then there is an auto generated HTML
documentation that
gives you the reference, what each
bit exactly means.
And there is also an auto generated USSI
database that can be used in other tools
like Arachne to
do something with this kind of FPGA.
And you have a couple of screenshots from
this documentation.
So on the on the lower left,
you have some of the written
documentation that covers.
This is actually from the from the I o
tile. And you see the column
PAFA control bits that
are used for the overnight's and stuff
like that is documented here.
Then the two
screenshots with this this, this
wonderfully colored table,
this the automated generated
HTML documentation where we
document the function of each and every
individual bit, and most
of them in more than than just
one way. So we have
in this case some some matrices
that can tell us which nets
can be connected to each other.
That and what bits are
used for that.
And here on the apparatus, actually, see
for for one logic, Tildy, the entire
collection of bits, we have a reverse
engineer.
So you see there are some
you see there are some some gray areas.
And as far as I
can tell, it's not the things that I have
missed, but these bits are just not
used.
I can't be sure, of course, but I didn't
manage to create any
design that would use those bits, so I
think it's a pretty fair guess that
they actually are unused.
And on the on the bottom right, you see
a part of the interconnect documentation
and you can can see things like
this. This interconnect
lines are crossed out and
stuff like that.
So it took us quite a while
to to figure out all these details.
Yeah, so that's that's project I assume
that's the low level stuff.
And of course, it's very interesting to
just see how the FPGA works and to
know what each and every individual does.
But this doesn't really give us something
that we can can use for like like
everyday design work with with
FPGA.
So part two of
this is the place untruthful
that Cottonseed wrote
this now takes this place Netlist
and convert it into one of those text
files.
So it performs essentially
this operations here, it
instantiates I oversells.
And this is more like a convenience
feature, but it's something that is quite
useful for our place and throughout
low level implementation tools to do
something like that, it packs
looks and Carol Logic's and flipflop
instances into isolated logic
cells because the architecture Netlist
has individual lookup tables and
carry logic blocks and flip flops
and we need to figure out how
we can fit them into
this logic cells,
then replace the design.
This is currently done by simulated
annealing only, but we are
walking on the floor that that
would use like a
first step that.
That does an analytical placement and
then we refine it using simulated
annealing, then, of course, throughout
the design and then it comes to the FPGA
config.
So how does this input Netlist
format will look like this display file?
We use the same cell types that
are used for the by the
latest twist themselves.
So we will stick to the ice for the
technology library, which
allows us to to mix our
own toolchain with the letters to change
and for example, use use our front
end and then go into the letters
background or vice versa.
Cliff is a pretty easy file format, and
you see a simple example
here.
Model is just a statement for.
Lefkow is a model, but
you would see a model
and then you have a list of inputs and
outputs, every nets that are used
but not delivered as inputs and outputs
are just internal wires.
And in this case, the entire design is
just a simple lookup table,
essentially spelled out for
with this for inputs and outputs.
And here you see are nonstandard
statement that is used to set the
lookup table for for this
particular lot, for instance.
But it can also put
additional input files into the ice
storm flow, for example, you can
give it the physical constraints file, as
I mentioned already, that is primarily
used for your placement.
And once again, we try to
do something that looks very similar to
the file formats used by the latest
tools. So it's easy to
to switch between back and forth between
our two tuition and the latest, which
you can also use a place and throughout
script. This is more experimental feature
that is in development right now.
They can manually
specify what steps should
be taken in which order and also
give the individual additional
parameters.
And with that, we have already
an experimental flow of very used
to analytical plays and uses together
with Arachne.
But that's not actually what I would like
to do in the analytical placement,
because the analytical placement uses
doesn't really know how
the speech looks like
and that there are only certain places
where tile can go, for example.
The output format of the panel on the
other side of this system,
ASCII files, and as I've said, they can't
be converted to
the things that you would like to do with
them, with the some
low level tools.
But of course, you can also create
additional outputs like placement
file that contains all
the placement of the generated
automatically during a placement
or that list of, for
example, the PECT design,
because this is something that you might
want to investigate.
So this is the second
part of our Floreana.
Now we can take
a technology Netlist and actually
implement it on the
the the
chip. So
theoretically, we could already create
very minimalist designs.
But it's not not not
how you would like to do it.
So in the third part, we're going
to look at users and users, as I've said,
is my my main project.
It's the tool that can
actually take HDL designs written in
the airlock and convert them to
whatever you would like to use in the
end.
So this is a small excerpt of
what you can do with yourself.
You can read various file formats and
most importantly, you can read
via Hallock. And in this case, the analog
is pretty much everything from the analog
2005.
So it's
pretty much up to date.
However, as you can see, there is no
visible front and at the moment
are people who are saying they would like
to work on that.
And I am very curious
to find out what what
we'll see in a year or so.
You can write various file formats.
Of course, you can write off that list,
which can be interesting for things like
post synthesis simulation.
But you can also write Beliefnet list.
You can write it if not list, which
is very important if you would like to
go into a commercial account, because
they usually use it as
an interest exchange format and some
other format, you can
of course, perform RTL
synthesis and also logic
optimization.
Some of the optimization is done and uses
directly and some of the optimization
uses an external tool from the
university called ABC, which is
used for like low level logic
optimization.
And you can, of course, map the science
to target architecture like
certain FPGA architect architectures
or Excel libraries, and
you can also perform far more
verifications, which is
actually the thing I maybe spent most
time on working.
Some have said that uses something
like LGM for hardware.
I really like this this idea
and I like this analogy.
But there are a couple of
projects at the moment that try to become
the LVM father,
so I can't really claim the title yet.
So what what kind of laws to really
exist? Of course, there exist many
more laws that are implemented with
users, but most of them are like
one one person
building a custom floor, which is part of
the season's work or something like that.
So these are the floors that
are like more general and something
that that that you actually
might want to use.
As it is, there
are two floors that use yourselves
as front end desk floor.
And there's is, too.
And both of them have been
already used to tape out chips
for Q4.
I also know that people have taped
commercial ships with that.
So this is something that is actually in
use and it's not like a thought
experiment. And theoretically, they could
it's actually done.
Then, of course, there is the synthesis
files for the FPGA,
which is the floor I'm talking about
right now.
And then there is a floor for exiling
seven series FPGA.
But with that flow, we don't have
any open source implementation backend
to do things like place handwrote.
So you could use
users to do the synthesis, but then you
would still need to use something like
Tydings Movado to to do the actual
implementation.
And of course, there are a few former
verification floors, and
I think the most interesting
one is yours as S.A.
BMC that used
to perform former
verifications using standalone
S.A. solvers by writing
files in S.A.
to format and doesn't to is the format
that is used for the competitions before
asanti solver.
So this means you have no vendor
lock in whatsoever because
every S.A.S.
solver that is going to be written
will support the Assante to file format
because they want to compete in these
competitions.
So what does Yosses syntheses
script look like and
that something like this here
you have a usually generic part
that is just read this design files
and then some kind of synthesis
comment that is here,
the very generic comment.
And then you have a target specific part
that does the mapping to the target
architecture in this case.
And they sell library.
But, of course, this this looks very much
like it looks when when you're looking to
commercial lasic floors,
they usually look quite similar that
you have something like a script and it
reads a few files and
then it calls one command that does
the magic synthesis part,
but then uses this command is
actually a script itself that is just
a sequence of other comments.
And then you look into the health message
for the CENTCOM and then you see
this, the script that is actually used
behind the scenes.
And some of those comments like Pork
Opt or FSM or memory
are themselves just sequences of
other comments.
So it's quite easy to to
look at this and actually understand what
what steps are taken in sequence
to a high level description of
a design into a low level necklaced
for the given target architecture and
is, of course, also possible to do things
like stop synthesis at any given
point here, and then dump this
intermediate netlist and see what what's
going on.
Yeah, as I've mentioned already,
a formal verification of something that
is very important for me,
so I have to have a slightly
different form of verification
methods that can be used with users.
There is a built in sova
that can be used to answer simple
questions, like is there any sequence
of of of
of any time steps
where in the end the
signal is high and the signal B is
low and then it will try to find such
a sequence.
I actually used this quite a lot
when when, when doing larger FPGA
designs than you have to instrument
and something like debugger.
And you only can have so
many signals that you look at and you
want to back. So you end up with
debug trace that say something like, oh,
this signal is high and the signal is low
in that time to look at this and you
wonder how is this even possible?
I don't see how this is possible.
And usually you would need to
recent the size, the entire design.
I'd add more signals to to find
out what happened to those signals so
that they end up in this state.
But with this technology, you can just
take the design and say, I have observed
that these two signals go to
the states.
What can cause this?
And it will give you an answer.
There is a large framework for
equivalence checking, which is very
important if you do things like writing a
synthesis tool, because you would like to
make sure that the output of your
synthesis tool is formally equivalent to
the input. So I added
that you can do
a property
check and using meter circuits with the
built in solvent with external solvers
like in ABC, the soldiers that can
be used for that.
And of course there is this uses S&P, BMC
flow that I mentioned before.
So this is this is the
floor with these three tools,
we can we can implement everything
we we
we need we can we can build the signs.
So so how do we do this?
First, we need the development board
and luckily there are a lot of
development paths available.
So let us know if you
want.
But there are also a lot of development
parts and I'm not sure
what's the percentage of them that have
been inspired by the availability of
this open source floor,
which of those have been planned
already before I published
my book?
But in the lower
left corner, you see the Ichabod and the
Ichabod's is actually a project I'm
involved with, so I'm going to use
that for for the demo.
This is the Ichabod.
It's a Raspberry Pi hat featuring
the eight K FPGA,
and it supports up to 20 pimlott
parts. Then when you use
extensions, balls that are connected to
the flat flex connectors.
So in total, you have almost
200 eye opens on the respray with that.
And I think this is something that can be
useful even if you're not really
interested in an open source FPGA
toolchain.
So there are a couple of applications.
Of course, you can just make an
intelligent Raspberry Pi expander
that a little bit more than just
exposing eyeballs.
You can use the Raspberry Pi as a network
Navot program and debugger,
which is quite useful.
And one bad idea that I
like very much as you can actually
create HDL called on the fly
on the Raspberry Pi and synthesize
it on the Raspberry Pi and program
it into the FPGA without
going to any external workstation
that does the synthesis and bitstream
generation step for you.
So we've built a small demo, SLC,
and I have two motivations
for that. The first one is I would like
to convince you that this
toolchain can actually be used for
non-trivial designs and not
just small HelloWallet examples.
And the second thing is this is a very
small FPGA.
So I would like to convince you that even
with something that only has 8000
lots, you can do
interesting things.
So my time, my demo
of design here, my demo system
on a chip uses only about 50
percent of the logic resources on this
FPGA.
So it could also be very interesting
as a basis for other projects because I
still have half of the device for
whatever you would like to add.
And it includes a full feature,
32 bit processor that's
compatible with the risk.
Five instructions set so you can use
Jesusita, which can and stuff like that
to to build
programs for that.
And in this demo, the Raspberry Pi
is only used as a network enabled
debugger and to access the console
part of the system on a chip.
It doesn't do anything else.
So this is a simplified block diagram of
of my my demo,
you see all
the things in pink
as something that runs on the FPGA
itself and you see the
external components are like the rest.
Rupi that's connected to this card
that implements
have two parallel communication
link between the Raspberry Pi and the
FPGA.
And I could goes to various endpoints
on the on the FPGA
there is an on chip debugger.
There is an endpoint that can be used
to upload programs into the FPGA
system. There is a text console,
stuff like that.
There is a two bit system
that connects all the components in the
system,
like all those endpoints.
Then the internal block memory,
the Eslam controller that connects to the
external externalism.
We have a frame buffer here to
talk to this lady matrix.
We have a controller to access
all the options.
We have, of course, the processor itself
and we have some some logic for clock
management.
So how do we synthesize something like
this in this case, we're just
using a makefile and
here are the relevant make holes
and you see the three steps that
I had already on the first slide.
I use Yosses to
read the
code, synthesize
it and write it into a play file.
Then they use Arachne to take that
file and the placement constraint file
and to turn it into a
text file, a text representation of the
FPGA bitstream.
And then they use icepack to conduct this
text representation into the actual
binary file that can be programed
into the FPGA.
Additional are macros.
When you look up the project
to to build the actual firmware and stuff
like that, using the risk five compiler
toolchain and also additional
macros for
for programing.
And there is a tool
called I could block that runs on the
Raspberry Pi and we can either run it
locally in that case as
each recipe is just as dachsie.
So it's just using a shell
to stop this program locally.
But as I say, each recipe can also be
just a call to SNH to
use as a sage to connect to
to the Raspberry Pi.
And I could always read from an input
and output so I can use just standing
out for things like I'll use
this binary and write it into
the flesh in this
case.
Yeah, also mentioned the Onchi
Baracoa, so
you can just hook it up to to
any nets you would like in your design
and essentially get the logic.
Analisa, you can write a few lines
of code to find your
trigger condition and to
define what clock cycles you would like
to keep in memory and
what clock cycles you would like to
ignore.
And with the deep myth, the default
environment, I have to make target called
make debark that just connects to the
widespread viruses and downloads
velia change stamp file that can be
displayed in the program like like TDK.
Yeah, running applications on
the system on a chip
looks like this year
when it first starts, you see the
bootloader running and to put
this place, this image of a floppy disk
you see on the left, because that's where
I think it should display.
Then a couple of examples
of programs that I wrote.
And they just use this text console
to talk to the bootloader and
write a text representation
of the hex of content
to to the bootloader.
And that writes it into the assignment
and executed.
Yeah. And I'd like to to to try that
on.
Mhere.
It's.
So.
Yeah, something that, um.
So, uh, oops.
Um, let's just,
uh, uh.
These are put.
So.
That's taking too long.
That's exactly what they wanted to avoid.
Oh,
OK.
So.
Luckily, I didn't suspect the software
problem, so now we should see the
bootloader, OK?
And let me just.
Make this a little bit smaller, so.
And then let's, for example,
do this show.
So.
So now we have hopefully
started something.
Unfortunately, can't go on because I
don't have it here.
Good.
OK,
so now we have this Christmas tree
blinking.
Let's go back to the FPGA director and
say make the book.
Um, so now we've downloaded
256 sightings of tieback
data from the Pilton debugger,
and we can just display this,
uh.
So.
So what's now?
Well, let's get.
OK, second
time it works. So now we have downloaded
something like that, and in this case I
have configured the built in debugger
to to monitor the memory posts
in the things we can see, the instruction
features and and every
now and then probably an instruction
fetch.
How do I.
OK. All instruction fetches 256
cyclists, not so much.
Uh.
OK, so we can see this is,
I think, really a nontrivial
system and
and shows that we have a toolchain
that can be used to do real world stuff
and not just very simple Healthwatch
like things.
OK, good.
Uh.
So how does it compare to the commercial
flow?
So there are two commercial flows
available from from Lettice.
They both use the letters
proprietary picante.
SBT beckoned.
But one of the two floors
is using simplifier pull as syntheses
front and the other one is using
Lettice LC as a system.
This is Fronton and we are comparing that
with Yosses and the
first couple of notes for this.
I'm using a version of the
latest tools that there's always almost
a year old. And the reason is that I have
wasted a day of my life
trying to activate the license for a
newer version and failed.
So I'm not sure how
it would compare with the uptodate
version of the lattice floor.
And the second thing is that
users might not be so good
when you look at logic optimization
and what you can do with the mappings.
But the audience is astonishingly
good with inferring memories
from behavioral code, in many
cases better than than
the many commercial tools.
And this is also the case here.
So when I used my design as
it was with the users, I
had something like 20 to placoderms,
but the other two toolchain
had also seven and eight blockhouse like
here but but like 80000
lookup tables because they are
back to it using
the Dealogic resources
to implement those memory resources
because they didn't know how to do things
like in from memory with byte.
And the rights are
in for memories with complex
and Abers and
the information architecture.
This is not a problem, but with the
ISO, the FPGA.
So you have to have an output register on
the block. So don't correctly infer
that with a neighbor you just can't use
the block business anymore.
So instead of
rewriting the entire design,
so it works on all three toolchain,
I made a stripped down version that's
not using the frame buffer because
blocking and resources
make some troubles.
And I also stripped down the internal
block to like for the arts or something
like that.
So it would be implemented
in logic. In both cases
you can see in terms
of packed logic cells,
the users are actually Penaflorida is a
little bit compared to the other
two floors, but it's not like the
world.
And the main reason for that is that
users at the moment too aggressive with
using the Kerry logic.
So you see we have almost
500
cells used and the other flows
only used three hundred and seventy two.
Because I'm too aggressive with
instantiating carry cells.
I often times a
fast a very, very small logic path
to one side of the carousel and another
logic path and the other side of the
carousel, and I end up with a
higher logic utilization.
So that's the main reason why why we
have this is different here.
But I think it's not the not the world.
But I find quite interesting is that
synthesis is more or less the same
time for all three floors like
this. Alesi is actually a little bit
faster in this case, but
the implementation time is
much, much smaller,
which
is much faster than the
battery pack and.
And a lot of this
thank you.
And a lot of this is because of
time when the commercial tours are
like loading of
that ship configuration and stuff like
that, because we prickish that
when you have virtually empty design
that just, I don't know, connect an input
directly to output, there's nothing else
you can create a bitstream in under a
second or maybe a second and a half.
So after a couple of links and
if you would like to scan this and get to
the to the link for this presentation,
for all the other links to
the slides are already online
on this location.
And I'll see if I can
also link them in the in the
proceedings online.
But but if not, just go to at
papers and then you will probably find
the link to to this.
Yeah, so the people
working on that on different
parts, the list is, of course,
incomplete and a lot of people
who just
contributed very small but
very important things like small
test cases to the expose box
is something that is always very, very
welcome.
And you also have an assembly here.
So please visit us
one on one.
So between the blinking area and
until meet the left, it's near by the
podcast. Podcasters are that the 3D
printers are.
We have we have more apps on
this thing that you can play with if you
want.
And we are also going to to do
workshops today, tomorrow and the day
after tomorrow at nineteen hundred.
So if you'd like to
have a hands on experience with this kind
of flowed and then please come to
our desk and register for those
workshops, if a lot of
people would like to see this
and then we will probably schedule
more workshops.
Yeah. And we also give a Ichabod's if
you have a cool project that you
think that would be nice
to demonstrate what I
can do, then we are all for it
and we'll give you a board.
Yeah. Thank you.
All right, so we have a good
10 minutes of questions and
answers, time left.
So if you have questions for Clifford,
please come to one of the microphones
in the SOL.
So everybody, even the people
watching the video or the screen can hear
you.
Um, and while
you are lining up at the microphones, we
are going to start with a question from
the signal, please.
Thank you, A.J., and wants to know he
has a question about partial
reconfiguration of space
with higher amount of gates.
Just the icy letters series have
internal configuration parts like
the Sitings FPGA do.
Short answer, no, there is
nothing that you can do for a partial
reconfiguration.
However, there is an
internal report card called WARMBLOOD
that can be used to reconfigure the
entire FPGA from
the FPGA. So it has to
select pins and one trigger pin.
And if you açaí the trigger pin,
then the to select Pennsville will
specify which of up to four
bitstream will be loaded in
the FPGA. So this is possible, but you
can partially reconfigure a device
while it's running.
OK, all right, then we're going to
go ahead with what
you said when you first started.
You got some emails about
the IP.
Have your relations with latish improved
since then?
Oh, it was not from from letters.
This was just just from er from a random
guy who, I don't know, saw
it on Hecate that that
I have done this and apparently
took it very personally and
thought I am after his IP
and so he sent me an email and
actually wrote that I should go to jail
for what I did.
It was quite an interesting experience.
OK, so we're going to mix in another
question from my Twitter.
Chris wants to know whether the error
messages are comprehensive.
For example, no resources left
or clock three is not feasible.
That's a good question.
I think for all stages
of of of the flaw, the error
messages could be better.
I know it in particular for users and
users, there is a lot of room
for improvement for things like
the input is not actually called.
Usually you just get syntax
in line so-and-so and then maybe it's
plus or minus five lines because
that that's how parcels are.
So so the error reporting is not very
good, but
usually you get an error
that that with at least some some
experience you can.
Trek back to the problem.
OK, perfect, Mike five, please.
Yeah, I would like to know a little more
about the support.
So you mentioned it shortly, but still
a schedule one which will
be supported.
No, right at
the moment there is someone
working on it, but I think there is no
cold yet.
There are two two ideas
how to support Vittel.
One one is they could
buy the new Verdell front end.
And the student was interested
in inviting, if you still want to, is
going to follow this approach
to the other possibility would be to
use some kind of
translator.
And there is an interesting
project that is part of Eco's,
which is the LP,
which is a preprocessor to convert
behavior Verdell into behavior
via a lock. And when you do that, you
actually can't do that. You need to add
more features to to the analog because
the simulation models are a little bit
different. But with synthesized area
code, it should actually be possible to
convert synthesizer Vittel
the syntax very long.
So maybe it would be possible to, like,
hack this tool to
to do that.
But but I am personally not working
on either of those because I'm
totally happy to be idealogue,
but I think that's my personal preference
for it.
Another question from the Antwerp's
2000 wants to know how powerful is
your Processo from the demo
in terms of registers and memory?
OK, so it's a it's a risk five
processor.
And if you've never heard of Risk five
before, it's a really, really cool
project that aims at creating
an open instruction set architecture that
is free of any
IP claims.
So you can implement
powerful processes with
with with instructions that architecture.
The process I have here is obviously
to it's it's a project of mine and
it's not very powerful because it's
optimized for size.
So on here, I think
it's less than than two thousand
lookup tables on Xilinx
seven series, which is my my
prime target architecture for this
chip in the smallest configuration, it's
smaller than 750 lookup
tables.
So it's a really, really small processor,
but it will take
four cycles approximately for each
instruction. It varies a little bit.
On the good side, you can clock it with
up to four megahertz.
So a lot of FPGA processors
want go to something like 60 megahertz,
then it evens out a little bit.
Risk five is a little bit instruction
set. And regarding the registers attached
to general-purpose registers,
thirty one because one is a zero register
always has zero and rights to it
diagnosed.
OK, all right, we still have time left,
so we are going to go over to Mike for
the next question.
And totally happy to see that
such a accessible, open
project for teaching
children in school or a classroom,
how the
process works from community
policy, specification of the process at
all to put pens and allows
for very cheap people
to really understand says to teach this.
This is awesome.
And and I'm wondering,
you mentioned that an interest of yours,
especially this verification, and
I wonder whether this can be shown on
the on the level
of the process that you mentioned is a
real science. You could say, oh, my all
put pen on the process,
went to a high and low.
And can you can you verify
on that size
does happen verification
tasks that I can run on my processor.
Generally, processors
are hard to formally verify because there
is this huge divergence of
control flow inherently having a
processor.
But there are things that I do
like, as I've I think
mentioned, the processors
configurable. There are features you can
turn on and turn off and they have
a form of proof that says
when I have two sets of of of
features and
the and I only look at
sequences of instructions that don't
let the less powerful
features that processor trap
then give more power for must always
have the same behavior.
And this is a kind of proof that I can
actually do with Mafiosos right now.
OK, before we go to the next question,
just a quick ask to the people in
the room coming in or leaving, please be
as quiet as possible so we can
finish the Q&A.
Mike five, please.
I want to say thank you very much for
doing this work to you and to
cottonseed, I think this is this
is the equivalent of the first version
of GCSE, but for
hardware.
So thank you very much for that.
Thank you.
All right, then we'll just stay with my.
Yeah, great project, but
what about timing,
validation and timing
during Disenrolled?
Yeah, right now none
of our processes are really timing
driven. There are some some very
weak timing driven optimizations and the
high level stuff just know it's better to
do this structure right instead of the
things like that.
Right now, the place and stuff is not
timing driven because we are still
working on uncrating timing
models.
But this is almost finished.
There are some
technical difficulties.
I think it's not not the right
moment now to the custom, but
I invite you to come to our assembly
and I would be happy to talk about it.
All right, then we're going to give the
people who are not able to be in
the room and the chance to
ask thank you, how does let us think
about your open source floor.
Are you in contact and what's coming
next?
Yeah, I don't know
if anyone from lettuce is here, please.
I would like to reach out to lettuce
as soon as I have a walking timing
flow, because that's the one thing
that's still missing right now.
And in my experience with all these
projects, with yours and all the other
stuff, whenever I approach
some kind of commercial entity, they
just don't believe that I can do
what I say I will do.
So I would like to have complete floor
that is really production right there and
then say, here it is.
Maybe you would like to work with me
together to improve on
it.
OK, two more minutes, so to
get as many questions in as possible,
please make it short and precise, Mike,
to please.
Do you think it would be feasible to
design and fabricate a
independent FPGA that would be compatible
with this file format using
open micro libraries?
I think it would be possible,
but it
would be not
really much harder to just make your own
FPGA design and use these tools
and create a database similar to
the database we are using here
and things like that.
And there are actually
projects going on right now.
We're thinking about doing stuff like
that, creating our own FPGA.
So for me, this
is of course interesting to really have
support for an FPGA, but it
was also important.
So I can just show that my thoughts
and can can deliver.
Over 10 years ago, I tried to approach
some companies and
convince them to build an open source
FPGA and essentially all that openness.
It's completely impossible because we
will never have to open source toolchain
now we have to open source toolchain so
I can go back to that and see if
we can get an open source FPGA
fabricated, OK.
And I think our last question is coming
from someone watching the stream.
Again, I actually have two.
One is can you run over on OS?
And the second one is what you think it
would be possible to leverage your work
on the FPGA device to reverse engineer
other devices?
How would approach look like?
I looked into the data on
each day and decided I can process
them with the dialog in
the default configuration, they
would like to use multiplier
primitivist of exiling specific.
So that would be something that
would lead some changes.
But but it should be possible.
And, A.J., I think we should also
be large enough for
the one thing.
I didn't really get the second part of
the question, but I think we're out of
time anyway.
But you had your contact details.
So people here who still have
questions and also people from the
Internet can probably get in contact with
you. So thanks for the
talk. Thanks for the people asking.
Thanks for having me.